Semiconductor device and method for producing it

ABSTRACT

Disclosed is a bottom-gate-type semiconductor device comprising crystalline semiconductor layers, in which the source/drain regions each have a laminate structure comprising a first conductive layer (n+ layer), a second conductive layer (n −  layer) of which the resistance is higher than that of the first conductive layer, and an intrinsic or substantially intrinsic semiconductor layer (i-layer). In this, the n − layer functions as an LDD region, and the i-layer functions as an in-plane offset region. The semiconductor device has high reliability and high reproducibility, and is produced in a simple process favorable to mass-production.

[0001] The present invention relates to a semiconductor device thatcomprises thin semiconductor films having a crystalline structure, andto a method for producing it. In particular, it relates to theconstitution of thin film transistors (hereinafter referred to as TFT)having an inverse stagger structure. It also relates to the constitutionof semiconductor circuits, electro-optical devices and electronicinstruments having those TFT.

[0002] The terminology “semiconductor device” referred to herein isdirected to any and every device that functions on the basis ofsemiconductor characteristics; and TFT, semiconductor circuits,electro-optical devices and electronic instruments referred to herein isall within the category of that terminology, semiconductor device.

BACKGROUND OF THE INVENTION

[0003] TFT have heretofore been being used as switching elements inactive matrix-type liquid crystal devices (hereinafter referred to asAMLCD). At present, devices with TFT circuits that comprise activelayers of amorphous silicon films have a high market share. Inparticular, inverse stagger structures capable of being produced insimple processes are much employed for constructing TFT.

[0004] With recent developments in high-quality AMLCD, however, TFT arebeing required to have much better operating characteristics (especiallyfor high operating speed). In such situations, amorphous silicon TFT areoften unsatisfactory as their operating speed is not high, andhigh-quality devices comprising amorphous silicon films are difficult toproduce.

[0005] Accordingly, polysilicon TFT have become much highlighted inplace of amorphous silicon TFT, and TFT comprising polysilicon films asthe active layers are being actively studied and developed in the art.At present, some polysilicon TFT devices are on the market.

[0006] Many reports have already been disclosed, relating to inversestagger-type TFT structures comprising active layers of polysiliconfilms. For example, referred to is a report of “Fabrication ofLow-Temperature Bottom-Gate Poly-Si TFTs on Large-Area Substrate byLinear-Beam Excimer Laser Crystallization and Ion Doping Method: H.Hayashi, et al., IEDM 95, pp. 829-832, 1995”.

[0007] In that report, they illustrated one typical example (FIG. 4) ofinverse stagger structures comprising polysilicon films. However,inverse stagger structures of that type (that is, so-calledchannel-stop-type ones) have various problems.

[0008] First, in those structures, the active layers having an overallthickness of 50 nm or so are extremely thin. Therefore, in those, impactionization at the junction of the channel-forming region and the drainregion is occurred, whereby the structures are significantlydeteriorated due to hot carrier implantation. For these reasons, a largeLDD region (light doped drain region) must be formed in thosestructures.

[0009] In this connection, the most critical problem is how to controlthe LDD region. The LDD region requires extremely delicate control ofthe impurity concentration therein and the length of itself. Inparticular, the length control of the region is problematic. At present,the length of the LDD region is defined by mask patterning. In fine TFT,however, any minor patterning error in masking the LDD region willproduce significant differences in TFT characteristics.

[0010] Another serious problem is that the sheet resistivity in the LDDregion significantly varies depending on the variation in the thicknessof the active layers. Moreover, the variation in the taper angle of thegate electrodes often causes the variation in the function of the LDDregion.

[0011] In addition, the LDD region requires patterning, which directlycomplicates the production process while lowering the throughput. It ispresumed that the production of the inverse stagger structure describedin the report noted above requires at least 6 masks (up to the step offorming the source/drain electrodes).

[0012] As mentioned above, the channel-stop-type inverse staggerstructure indispensably requires the transverse in-plane LDD region tobe formed at the both sides of the channel-forming region, in which,however, a reproducible LDD region is extremely difficult to form.

SUMMARY OF THE INVENTION

[0013] The subject matter of the present invention is to provide atechnique for producing highly-reliable and highly-reproduciblesemiconductor devices in an extremely simple process applicable tomass-production.

[0014] One aspect of the invention is a semiconductor device having asemiconductor film comprising a source region, a drain region and achannel-forming region, the semiconductor films having a crystallinestructure,

[0015] wherein the source region and the drain region each have alaminate structure comprising at least a first conductive layer, asecond conductive layer of which the resistance is higher than that ofthe first conductive layer, and a third semiconductor layer of which theconductivity type is the same as that of the channel-forming region, thelayers being laminated in that order toward the gate-insulating film.

[0016] In one embodiment of the constitution of this aspect, thesemiconductor film having a crystalline structure have a grain boundarydistribution peculiar to fusion-crystallized films.

[0017] In another embodiment, the concentration profile of the impurityconstituting the first and second conductive layers varies continuouslyfrom the first conductive layer to the second conductive layer.

[0018] In still another embodiment, the second conductive layer containsan impurity that varies continuously within the range of from 5×1017 to1×1019 atoms/cm3.

[0019] In still another embodiment, two offset regions each having adifferent thickness exist between the channel-forming region and thesecond conductive layer.

[0020] In still another embodiment, an offset region of which thethickness is larger than that of the channel-forming region existsbetween the channel-forming region and the second conductive layer.

[0021] Another aspect of the invention is a semiconductor device havinga gate electrode formed on a substrate having an insulating surface; asemiconductor film comprising a source region, a drain region and achannel-forming region, the semiconductor having a crystallinestructure; and a source electrode and a drain electrode as formed on thesource region and the drain region, respectively,

[0022] wherein the source region and the drain region each have alaminate structure comprising at least a first conductive layer, asecond conductive layer of which the resistance is higher than that ofthe first conductive layer, and a third semiconductor layer of which theconductivity type is the same as that of the channel-forming region, thelayers being laminated in that order toward the gate-insulating film,and

[0023] the source electrode and/or the drain electrode overlap(s) withthe gate electrode on the channel-forming region.

[0024] Still another aspect of the invention is a semiconductor devicehaving a semiconductor film comprising a source region, a drain regionand a channel-forming region, the semiconductor film having acrystalline structure,

[0025] wherein the source region and the drain region each have alaminate structure comprising at least a first conductive layer, asecond conductive layer of which the resistance is higher than that ofthe first conductive layer, and a third semiconductor layer of which theconductivity type is the same as that of the channel-forming region, thelayers being laminated in that order toward the gate-insulating film,and

[0026] wherein an HRD structure comprising two offset regions eachhaving a different thickness and the second conductive layer is formedbetween the channel-forming region and the first conductive layer.

[0027] In one embodiment of the constitution of this aspect, one of thetwo offset regions each having a different thickness is for offset inthe in-plane direction and is formed of a semiconductor layer of whichboth the conductivity type and the thickness are the same as those ofthe channel-forming region, while the other is for offset in thethickness direction and is formed of a semiconductor layer of which theconductivity type is the same as that of the channel-forming region butof which the thickness is larger than that of the channel-formingregion.

[0028] Still another aspect of the invention is a method for producing asemiconductor device, which comprises the steps of;

[0029] forming a gate electrode, a gate-insulating layer, and anamorphous semiconductor film on a substrate having an insulatingsurface,

[0030] exposing the amorphous semiconductor film to laser beams or tointense light equivalent to laser beams to thereby convert it into asemiconductor film having a crystalline structure,

[0031] adding an impurity selected from Group 15 only or from Group 13and Group 15 to the semiconductor film having a crystalline structure toform conductive layers,

[0032] forming a source electrode and a drain electrode on theconductive layers, and

[0033] etching the semiconductor film having a crystalline structure viathe source electrode and the drain electrode both acting as masks forthe film to thereby form a channel-forming region.

[0034] Still another aspect of the invention is a method for producing asemiconductor device, which comprises the steps of:

[0035] forming a gate electrode, a gate-insulating layer, and anamorphous semiconductor film on a substrate having an insulatingsurface;

[0036] irradiating the amorphous semiconductor film with laser beams orto intense light equivalent to laser beams to thereby convert it into asemiconductor film having a crystalline structure,

[0037] adding an impurity selected from Group 15 only or from Group 13and Group 15 to the semiconductor film having a crystalline structure toform conductive layers,

[0038] forming a source electrode and a drain electrode on theconductive layers,

[0039] etching the semiconductor film having a crystalline structure viathe source electrode and the drain electrode both acting as masks forthe film to thereby form a channel-forming region, and

[0040] adding to only the channel-forming region an impurity forthreshold voltage control, via the source electrode and the drainelectrode both acting as masks for the region.

[0041] Still another aspect of the invention is a bottom-gate-typesemiconductor device having a semiconductor film comprising a sourceregion, a drain region and a channel-forming region, the semiconductorfilm having a crystalline structure,

[0042] wherein the semiconductor film has a grain boundary distributionpeculiar to fusion-crystallized films, and

[0043] wherein the source region and the drain region each have alaminate structure comprising at least a first conductive layer, asecond conductive layer of which the resistance is higher than that ofthe first conductive layer, and a third semiconductor layer of which theconductivity type is the same as that of the channel-forming region, thelayers being laminated in that order toward the gate-insulating film.

[0044] Still another aspect of the invention is a bottom-gate-typesemiconductor device having a semiconductor film comprising a sourceregion, a drain region and a channel-forming region, all ofsemiconductor layers having a crystalline structure, wherein;

[0045] the semiconductor layers have a grain boundary distributionpeculiar to fusion-crystallized films,

[0046] the source region and the drain region each have a laminatestructure comprising at least a first conductive layer, a secondconductive layer of which the resistance is higher than that of thefirst conductive layer, and a semiconductor layer of which theconductivity type is the same as that of the channel-forming region, thelayers being laminated in that order toward the gate-insulating film,and

[0047] the concentration profile of the impurity constituting the firstand second conductive layers varies continuously from the firstconductive layer to the second conductive layer.

[0048] Still another aspect of the invention is a bottom-gate-typesemiconductor device comprising a source region, a drain region and achannel-forming region, all of semiconductor layers having a crystallinestructure, wherein;

[0049] the semiconductor layers have a grain boundary distributionpeculiar to fusion-crystallized films,

[0050] the source region and the drain region each have a laminatestructure comprising at least a first conductive layer, a secondconductive layer of which the resistance is higher than that of thefirst conductive layer, and a semiconductor layer of which theconductivity type is the same as that of the channel-forming region, thelayers being laminated in that order toward the gate-insulating film,and

[0051] the second conductive layer contains an impurity that variescontinuously within the range of from 5×1017 to 1×1019 atoms/cm3.

[0052] Still another aspect of the invention is a bottom-gate-typesemiconductor device comprising a source region, a drain region and achannel-forming region, all of semiconductor layers having a crystallinestructure, wherein;

[0053] the semiconductor layers have a grain boundary distributionpeculiar to fusion-crystallized films,

[0054] the source region and the drain region each have a laminatestructure comprising at least a first conductive layer, a secondconductive layer of which the resistance is higher than that of thefirst conductive layer, and a semiconductor layer of which theconductivity type is the same as that of the channel-forming region, thelayers being laminated in that order toward the gate-insulating film,and

[0055] two offset regions each having a different thickness existbetween the channel-forming region and the second conductive layer.

[0056] Still another aspect of the invention is a bottom-gate-typesemiconductor device comprising a source region, a drain region and achannel-forming region, all of semiconductor layers having a crystallinestructure, wherein;

[0057] the semiconductor layers have a grain boundary distributionpeculiar to fusion-crystallized films,

[0058] the source region and the drain region each have a laminatestructure comprising at least a first conductive layer, a secondconductive layer of which the resistance is higher than that of thefirst conductive layer, and a semiconductor layer of which theconductivity type is the same as that of the channel-forming region, thelayers being laminated in that order toward the gate-insulating film,and

[0059] an offset region of which the thickness is larger than that ofthe channel-forming region exists between the channel-forming region andthe second conductive layer.

[0060] Still another aspect of the invention is a bottom-gate-typesemiconductor device comprising;

[0061] a gate electrode formed on a substrate having an insulatingsurface,

[0062] a source region, a drain region and a channel-forming region, allof semiconductor layers having a crystalline structure,

[0063] and a source electrode and a drain electrode as formed on thesource region and the drain region, respectively, wherein;

[0064] the semiconductor layers have a grain boundary distributionpeculiar to fusion-crystallized films,

[0065] the source region and the drain region each have a laminatestructure comprising at least a first conductive layer, a secondconductive layer of which the resistance is higher than that of thefirst conductive layer, and a semiconductor layer of which theconductivity type is the same as that of the channel-forming region, thelayers being laminated in that order toward the gate-insulating film,and

[0066] the source electrode and/or the drain electrode overlap(s) withthe gate electrode on the charnel-forming region.

[0067] Still another aspect of the invention is a bottom-gate-typesemiconductor device comprising a source region, a drain region and achannel-forming region, all of semiconductor layers having a crystallinestructure, wherein;

[0068] the semiconductor layers have a grain boundary distributionpeculiar to fusion-crystallized films,

[0069] the source region and the drain region each have a laminatestructure comprising at least a first conductive layer, a secondconductive layer of which the resistance is higher than that of thefirst conductive layer, and a semiconductor layer of which theconductivity type is the same as that of the channel-forming region, thelayers being laminated in that order toward the gate-insulating film,and

[0070] an HRD structure comprising two offset regions each having adifferent thickness and the second conductive layer exists between thechannel-forming region and the first conductive layer.

[0071] In one embodiment of the constitutions noted above, one of thetwo offset regions each having a different thickness is for offset inthe in-plane direction and is formed of a semiconductor layer of whichboth the conductivity type and the thickness are the same as those ofthe channel-forming region, while the other is for offset in thethickness direction and is formed of a semiconductor layer of which theconductivity type is the same as that of the channel—forming region butof which the thickness is larger than that of the channel-formingregion.

[0072] Still another aspect of the invention is a method for producing asemiconductor device, which comprises;

[0073] a step of forming a gate electrode, a gate-insulating layer, andan amorphous semiconductor film on a substrate having an insulatingsurface,

[0074] a step of exposing the amorphous semiconductor film to laserbeams or to intense light of which the intensity is equivalent to thatof laser beams, to thereby crystallize the film into a semiconductorfilm having a crystalline structure,

[0075] a step of adding an impurity selected from Group 13 and/or Group15 to the semiconductor film having a crystalline structure through ionimplantation or ion doping, to thereby form first and second conductivelayers containing the impurity,

[0076] a step of exposing the conductive layers to laser beams or tointense light of which the intensity is equivalent to that of laserbeams, to thereby activate the impurity,

[0077] a step of forming a source electrode and a drain electrode on theconductive layers, and

[0078] a step of etching the semiconductor film having a crystallinestructure via the source electrode and the drain electrode both actingas masks for the film to thereby form a channel-forming region, andwherein;

[0079] the thicknesses of the first and second conductive layers arecontrolled by the concentration profile of the impurity.

[0080] Still another aspect of the invention is a method for producing asemiconductor device, which comprises;

[0081] a step of forming a gate electrode, a gate-insulating layer, andan amorphous semiconductor film on a substrate having an insulatingsurface,

[0082] a step of exposing the amorphous semiconductor film to laserbeams or to intense light of which the intensity is equivalent to thatof laser beams, to thereby crystallize the film into a semiconductorfilm having a crystalline structure,

[0083] a step of adding an impurity selected from Group 13 and/or Group15 to the semiconductor film having a crystalline structure through ionimplantation or ion doping, to thereby form first and second conductivelayers containing the impurity,

[0084] a step of exposing the conductive layers to laser beams or tointense light of which the intensity is equivalent to that of laserbeams, to thereby activate the impurity,

[0085] a step of forming a source electrode and a drain electrode on theconductive layers,

[0086] a step of etching the semiconductor film having a crystallinestructure via the source electrode and the drain electrode both actingas masks for the film to thereby form a channel-forming region, and

[0087] a step of adding to the channel-forming region an impurity forthreshold voltage control, via the source electrode and the drainelectrode both acting as masks for the region, and wherein;

[0088] the thicknesses of the first and second conductive layers arecontrolled by the concentration profile of the impurity.

BRIEF DESCRIPTION OF THE DRAWINGS

[0089]FIG. 1A to FIG. 1D, and FIG. 2A to FIG. 2C show a process forproducing a thin film transistor in Embodiment 1.

[0090]FIG. 3 is an enlarged view showing the constitution of the thinfilm transistor in Embodiment 1.

[0091]FIG. 4 is a graph showing an impurity concentration profile in asemiconductor film in Embodiment 1.

[0092]FIG. 5A to FIG. 5C show the constitution of a thin film transistorin Embodiment 2.

[0093]FIG. 6A to FIG. 6C show the constitution of a thin film transistorin Embodiment 3.

[0094]FIG. 7A and FIG. 7B show the constitution of a thin filmtransistor in Embodiment 4.

[0095]FIG. 8 shows the constitution of a CMOS circuit in Embodiment 5.

[0096]FIG. 9 is a graph showing impurity concentration profiles in asemiconductor film in Embodiment 5.

[0097]FIG. 10A and FIG. 10B shows the constitution of a thin filmtransistor in Embodiment 7.

[0098]FIG. 11A to FIG. 11C show the constitution of a CMOS circuit inEmbodiment 8.

[0099]FIG. 12A to FIG. 12D, and FIG. 13A to FIG. 13C show a process forproducing a semiconductor circuit in Embodiment 10.

[0100]FIG. 14A and FIG. 14B show the constitution of a pixel matrixcircuit in Embodiment 10.

[0101]FIG. 15A to FIG. 15D show a process for producing a semiconductorcircuit in Embodiment 11.

[0102]FIG. 16 show sa process for producing a semiconductor circuit inEmbodiment 12.

[0103]FIG. 17A and FIG. 17B show a process for producing a semiconductorcircuit in Embodiment 13.

[0104]FIG. 18A and FIG. 18B show the constitution of a pixel matrixcircuit in Embodiment 14.

[0105]FIG. 19A and FIG. 19B show the constitution of a pixel TFT inEmbodiment 15.

[0106]FIG. 20 shows the constitution of a pixel TFT in Embodiment 16.

[0107]FIG. 21 shows the constitution of a pixel matrix circuit inEmbodiment 16.

[0108]FIG. 22 shows the constitution of a pixel TFT in Embodiment 17.

[0109]FIG. 23 shows the constitution of an external terminal connectingsite in Embodiment 18.

[0110]FIG. 24 shows a means of exposing a semiconductor circuit inEmbodiment 19.

[0111]FIG. 25A and FIG. 25B each show the constitution of anelectro-optical device in Embodiment 20.

[0112]FIG. 26A to FIG. 26F show outlines of various electronicinstruments in Embodiment 21.

[0113]FIG. 27A and FIG. 27B show the pattern constitution of asemiconductor circuit in Embodiment 22.

[0114]FIG. 28A and FIG. 28B show the pattern constitution of asemiconductor circuit in Embodiment 23.

[0115]FIG. 29 shows the constitution of a multi chamber in Embodiment24.

DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

[0116] The following Embodiments are to demonstrate preferredembodiments of the invention having the constitution noted above, which,however, are not intended to restrict the scope of the invention. Inthose, referred to are FIG. 1 to FIG. 29.

[0117] [Embodiment 1]

[0118] This is to demonstrate one typical embodiment of the inventionwith reference to FIGS. 1A to 3. First referred to are FIG. 1A to FIG.1D and FIG. 2A to FIG. 2C which illustrate a method for producing thesemiconductor device of the invention. As illustrated, a undercoatingfilm 102 of an insulating film comprising mainly silicon is formed on aglass substrate 101 to prepare a substrate having an insulating surface.A gate electrode (first wiring) 103 of a conductive film is formed onthe film 102.

[0119] The line width of the gate electrode 103 is from 1 to 10 m(typically from 3 to 5 m ). The thickness thereof is from 200 to 500 nm(typically from 250 to 300 nm). In this Embodiment, used is an aluminumfilm (containing 2 wt. % scandium) having a thickness of 250 nm to formthe gate electrode having a line width of 3 m.

[0120] As the gate electrode 103, also usable is any of tantalum,tungsten, titanium, chromium, molybdenum, conductive silicon, metalsilicide or their laminates, in place of aluminum. The aluminum film ispatterned (first patterning to form the gate electrode).

[0121] Next, the gate electrode 103 is subjected to anodic oxidation toform an oxide film 104 having a thickness of from 50 to 200 nm(typically from 100 to 150 nm). The oxide film 104 is to protect thegate electrode. In this Embodiment, the anodic oxidation is performed inan ethylene glycol solution containing 3% tartaric acid (this isneutralized with ammonia) at a voltage of 80 V and a formation currentof from 5 to 6 mA. The oxide film thus formed may have a thickness ofabout 100 nm or so.

[0122] Next formed is a gate-insulating layer comprising a siliconnitride film 105 (having a thickness of from 0 to 200 nm, typically from25 to 100 nm, but preferably 50 nm) and a silicon oxynitride or siliconoxide film 106 of SiOxNy (having a thickness of from 150 to 300 nm,typically 200 μm). In this Embodiment, the gate-insulating layerincludes the oxide film 104.

[0123] After the gate-insulating film has been formed, an amorphoussemiconductor film 107 comprising mainly silicon is formed over this. Inthis Embodiment, formed is an amorphous silicon film, which, however, isnot limitative. In place of the amorphous silicon film, also usable isany other compound semiconductor film (e.g., germanium-containingamorphous silicon film, etc.).

[0124] In this Embodiment, since a channel-etched bottom-gate-typestructure is formed, the amorphous silicon film 107 should be thick. Itsthickness may fall between 100 and 600 nm (typically between 200 and 300μm, but preferably 250 nm). In this Embodiment, the thickness of thefilm 107 is 200 nm. As will be mentioned hereinafter, the optimumthickness of the amorphous silicon film to be formed in this step willbe determined depending on the offset region and the LDD region to beformed in TFT of the invention.

[0125] In this Embodiment, the amorphous silicon film 107 is formedthrough low pressure thermal CVD. For this, it is desirable that theconcentration of impurities of carbon, oxygen and nitrogen isdrastically and severely controlled during the film forming step. Ifthose impurities exist and remain too much in the film formed in thisstep, they may have some negative influences on the uniformity of thecrystallinity of the crystalline semiconductor film to be formed fromthe film.

[0126] In this Embodiment, the impurity concentration is so controlledthat carbon and nitrogen are less than 5×1018 atoms/cm3 (typically notmore than 5×1017 atoms/cm3), and oxygen is less than 1.5×1019 atoms/cm3(typically not more than 1×1018 atoms/cm3). Under this control, theimpurity concentration to be finally in the channel-forming region ofTFT could be within the defined range.

[0127] As a result of these steps, obtained is the structure of FIG. 1A,which is then exposed to laser beams to thereby crystallize theamorphous silicon film 107. (FIG. 1B)

[0128] As the laser beams, a pulse-oscillation excimer laser may beemployed, for which is used KrF (248 nm), XeCl (308 nm), ArF (193 nm) orthe like as the excitation gas. In place of this, available are anyother various laser beams including Nd:YAG laser harmonics, etc.

[0129] For thick amorphous semiconductor films, as in this Embodiment,preferred are laser beams having a long wavelength as facilitatinguniform and entire crystallization of the films. Also preferred isadditionally heating the substrate at a temperature falling within therange between 50 and 500_C or so, during exposure to laser beams. Inconsideration of wavelength cycle of the laser beams to be used intoconsideration, still preferred is so controlling the thickness of theamorphous semiconductor film to be crystallized that the light absorbingefficiency of the film is increased.

[0130] In this Embodiment, pulse-oscillation XeCl excimer laser beamsare transformed into linear beams in an optical system, and scanned overthe amorphous silicon film 107 from one end of the substrate to theother end thereof, whereby the entire surface of the film 107 isannealed with the laser beams.

[0131] In this step, the oscillation frequency is 30 MHz, the scanningspeed is 2.4 mm/sec, the laser energy is from 300 to 400 mJ/cm2, and thesubstrate is heated at 400_C from its back surface. As a result of thisstep, formed is a crystalline semiconductor film (in this Embodiment,crystalline silicon film) 108.

[0132] Since the heat absorption differs between the amorphous siliconfilm and the glass substrate, the amorphous silicon film could beintensively heated if the upper surface of the film is exposed to laserbeams. In that manner, therefore, the amorphous silicon film could beheated at a temperature higher than the temperature that the glasssubstrate could bear (650_C or so).

[0133] Semiconductor films crystallized through exposure to laser beamssuch as that formed in this Embodiment (the semiconductor films of thattype are herein referred to as fusion-crystallized films) have a grainboundary distribution (existence distribution of grain boundaries)peculiar to laser crystallization. Observing the grain boundaries in thefilm through a known technique of secondary etching could definitelyclarify the crystal grains and the grain boundaries existing in thefilm, from which it is known that the film is an aggregate of crystalgrains having a grain size of from tens to hundreds nm.

[0134] On the other hand, semiconductor films crystallized by any othercrystallization means obviously differ from the fusion-crystallizedfilms in the mode of grain boundary distribution. This is because, inthe crystallization with laser beams (or with intense light of which theintensity is equivalent to that of laser beams), the semiconductorlayers being crystallized are once fused; whilst in the semiconductorlayers being crystallized by any other means, the grains grows in a modeof solid-phase growth. Thus, the crystallization mechanism of thisinvention differs from those of the any other methods.

[0135] Next, an element selected from Group 15 (typically phosphorus,arsenic or antimony) is added to the crystalline semiconductor filmthrough ion implantation (with mass separation) or ion doping (withoutmass separation). In this Embodiment, phosphorus is added to thecrystalline silicon film 108 while being so controlled that thephosphorus concentration in the depth that ranges between 30 and 100 nm(typically between 30 and 50 nm) from the surface of the film 108 mayfall between 1×1019 and 3×1021 atoms/cm3, but typically between 1×1020and 1×1021 atoms/cm3.

[0136] In this Embodiment, the region 109 thus formed in that mannernoted above to have such a high phosphorus concentration is referred toas an n+ layer (or a first conductive layer). The thickness of thislayer is defined to fall between 30 and 100 nm (typically between 30 and50 nm). In the present case, the n+ layer 109 will function later as apart of source/drain electrodes. In this Embodiment, the n+ layer isformed to have a thickness of 30 nm.

[0137] The region 110 to be formed below the n+ layer 109 has a lowphosphorus concentration, and this is referred to as an n− layer (or asecond conductive layer). In the present case, the resistance of the n−layer 110 is higher than that of the n+ layer 109, and the n− layer 110function later as an LDD region for field relaxation. In thisEmbodiment, the n− layer 110 has a thickness of 30 nm. The intrinsic orsubstantially intrinsic region 120 to be formed below the n− layer 110is referred to as an i-layer. In the i-layer 120, formed is achannel-forming region. (FIG. 1C)

[0138] In this step of phosphorus addition, the phosphorus concentrationprofile in the direction of the depth of the film 108 is of criticalimportance. This will be described with reference to FIG. 4. Theconcentration profile illustrated in FIG. 4 is for an example ofphosphine (PH3) addition as performed through ion-doping at anaccelerated voltage of 80 keV and an RF power of 20 W.

[0139] In FIG. 4, 401 indicates a crystalline silicon film, and 402indicates the concentration profile of phosphorus added to the film. Theconcentration profile is determined, depending on the defined conditionsof the RF power, the species of the ion added, the accelerated voltage,etc.

[0140] In the illustrated case, the peak of the concentration profile402 is inside the n+ layer 403 or around the interface of the n+ layer403, and the phosphorus concentration decreases more in the deeper siteof the crystalline silicon film 401 (that is, in the site nearer to thegate-insulating film). In this, the phosphorus concentration variescontinuously throughout the inside of the film, and therefore, the n−layer 404 is always formed below the n+layer 403.

[0141] Also inside the n⁻ layer 404, the phosphorus concentrationcontinuously decreases. In this Embodiment, the region in which thephosphorus concentration is over 1×10¹⁹ atoms/cm³ is considered as then⁺ layer 403, while that in which the phosphorus concentration fallswithin the range between 5×10¹⁷ and 1×10¹⁹ atoms/cm³ is as the n⁻ layer404. However, since no definite boundary exists between the layers 403and 404, the phosphorus concentration range noted above may be a roughcriterion for those layers.

[0142] The region having a greatly lowered phosphorus concentration andthe layer below the region constitute an intrinsic or substantiallyintrinsic region (i-layer) 405. The intrinsic region is a region towhich no impurity is intentionally added. The substantially intrinsicregion indicates a region in which the impurity concentration (thephosphorus concentration in this Embodiment) is not higher than the spindensity of the silicon film, or a region having an impurityconcentration of from 1×10¹⁴ to 1×10¹⁷ atoms/cm³ and exhibiting oneconductivity.

[0143] The intrinsic or substantially intrinsic region of that type isformed below the n⁻ layer 404. However, the i-layer 405 is basicallyformed of a semiconductor layer of which the conductivity is the same asthat of the channel-forming region. In other words, where thechannel-forming region is of a weakly n-type or p-type, the i-layer hasthe same type of conductivity as that of the channel-forming region.

[0144] As in the above, the ion implantation or ion doping to form then⁺ layer produces the n layer below the n⁺ layer. However, if the n⁺layer is formed according to a conventional film forming method, theconstitution of that type could not be realized. Where the conditionsfor ion addition are suitably defined, the thicknesses of the n⁺ layerand the n⁻ layer to be formed are easy to control.

[0145] In particular, the thickness of the n⁻ layer requires highlyaccurate control, as it is to be the thickness of the LDD region to beformed later. In ion doping or the like where the conditions for ionaddition are suitably defined, the ion concentration profile in thedepthwise direction of the film can be controlled accurately, and thethickness of the LDD region to be formed later is easy to control. Inthe present invention, the thickness of the n⁻ layer 110 is controlledto fall between 30 and 200 nm (typically between 50 and 150 nm).

[0146] The concentration profile illustrated in FIG. 4 is one attainedin one doping step. Apart from this, the doping step may be repeatedplural times to control the thicknesses of the n⁺ layer 403 and the n⁻layer 404. For example, doping at a high dose to produce the peak of theconcentration profile in a relatively shallow site where the n+layer 403is to be formed may be combined with doping at a low dose to produce thepeak of the concentration profile in a relatively deep site where the n⁻layer 404 is to be formed.

[0147] After the n⁺ layer 109 and the n⁻ layer 110 have been formed inthat manner noted above, they are again exposed to laser beams wherebythe impurity (phosphorus) added thereto is activated. (FIG. 1D)

[0148] Apart from laser annealing, also available for this is lampannealing (exposure to intense light) or furnace annealing (heating inan electric furnace). In the furnace annealing, however, the heatresistance of the glass substrate is taken into consideration.

[0149] In this Embodiment, the layers are subjected to laser annealingwith XeCl excimer laser beams. For this, the processing conditions maybe basically the same as those for the crystallization step noted above.In this, however, the laser energy may be from 200 to 350 mJ/cm²(typically from 250 to 300 mJ/cm²). During the laser annealing, thesubstrate is heated at 300_C from its back surface, whereby thephosphorus activation is promoted.

[0150] In the laser activation step, the crystalline silicon film 108damaged in the phosphorus addition step may be restored. In this step,the region of the film 108 made to be amorphous due to the ion collisionin the ion addition step may be recrystallized.

[0151] After the phosphorus activation step, the crystalline siliconfilm is patterned to form an island semiconductor layer 111. In thisstep, the length of the layer 111 in the direction vertical to thecarrier-moving direction in the final TFT to be produced herein (thislength corresponds to the channel width, W) is so controlled that itfalls between 1 and 30 _m (typically between 10 and 20 _m). The secondpatterning step is thus performed herein. (FIG. 2A)

[0152] Though not shown in the drawings, a part of the exposedgate-insulating layer is etched to form a contact hole (in the region118 in FIG. 2C), through which the gate electrode (first wiring) and theelectrodes to be formed in the next step (second wiring) areelectrically connected with each other. The third patterning step isthus performed herein.

[0153] Next, a conductive metal film (not shown) is formed, which isthen patterned to give the source electrode 112 and the drain electrode113. In this Embodiment, a three-layered laminate film of Ti (50 nm)/Al(200 to 300 nm)/Ti (50 nm) is formed. In this step, formed is the wiringfor electrically connecting the electrodes 112 and 113 with the gateelectrode. The fourth patterning step is thus performed herein. (FIG.2B)

[0154] As will be again mentioned hereinafter, the length of the region114 just above the gate electrode 103, or that as sandwiched between thesource electrode 112 and the drain electrode 113 (this region 114 isreferred to as a channel-etching region, and its length is indicated byC¹) will determine the length of the channel-forming region and that ofthe offset region to be formed later. The length C¹ may fall between 2and 20 m (typically between 5 and 10 _m). In this Embodiment, C¹=4 _m.

[0155] Next, the island semiconductor layer 111 is self-alignedlydry-etched via the source electrode 112 and the drain electrode 113 bothacting as masks. In this step, therefore, only the channel-etchingregion 114 is etched. (FIG. 2C)

[0156] In this etching step, the n⁺ layer 109 and the n layer 110 arecompletely removed, but the intrinsic or substantially intrinsic region(i-layer) only is not removed and remains as it is without being etched.In the present invention, only the semiconductor layer of being from 10to 100 run (typically from 10 to 75 nm, but preferably from 15 to 45 nm)in thickness remains as it is without being etched in this etching step.In this Embodiment, the semiconductor layer having a thickness of 30 nmremains as it is in this step.

[0157] After the island semiconductor layer 111 has been thus etched (inthe channel-etching step), a protective film 115 of a silicon oxide filmor a silicon nitride film is formed over this to obtain an inversestagger-type TFT having the structure shown in FIG. 2C.

[0158] In that condition, the region of the channel-etched, islandsemiconductor layer 111 that is positioned just above the gate electrode112 is a channel-forming region 116. In the constitution in thisEmbodiment, the width of the gate electrode corresponds to the length ofthe channel-forming region, and the length represented by Ll is referredto as a channel length. The regions 117 positioned outside the edges ofthe gate electrode 103 are outside the electric field of the gateelectrode 103, and are offset regions. The length of the regions 117 isrepresented by X¹.

[0159] In this Embodiment, the line width of the gate electrode 103(this corresponds to L¹) is about 2.8 _m in consideration of the anodicoxidation loss that gave the oxide film of 100 nm thick, and the length(C¹) of the channel-etching region 114 is 4 _m. In this, therefore, thelength (X¹) of each offset region is about 0.6 _m.

[0160] An enlarged view of the drain region (the semiconductor layercontacted with the drain electrode 113) is shown in FIG. 3. In FIG. 3,103 is the gate electrode, 301 is the channel-forming region, 302 is then⁺ layer (source or drain electrode), 303 and 304 are the offset regionseach having a different thickness, and 305 is the n⁻ layer (LDD region).

[0161] Though not shown herein, the source region (the semiconductorlayer contacted with the source electrode 112) has the same structure asabove.

[0162] The TFT structure is graphically drawn in FIG. 3, in whichspecial attention should be paid to the relationship between thethicknesses of the regions constituting the structure. In the mostpreferred constitution of the present invention, the constituent regionssatisfy the condition that the thickness of the n⁺ layer 302<that of then⁻ layer 305<that of the offset region (i-layer) 304.

[0163] This is because the n⁺ layer 302 functions only as an electrodeand may be thin. On the other hand, the n⁻ layer 305 and the offsetregion 304 should be satisfactorily thick for effective fieldrelaxation.

[0164] In the constitution of this Embodiment, the two offset regions303 and 304 each having a different thickness, and the LDD region 305exist between the channel-forming region 301 and the n⁺ region 302. Inthis, the region 303 is an offset region in the in-plane direction,which is formed by mask alignment, and this is referred to as a maskoffset region.

[0165] The region 304 is an offset region in the direction of thethickness of the film, and its thickness corresponds to the thickness ofthe i-layer. This is referred to as a thickness offset region. Thethickness of the thickness offset region 304 may fall between 100 and300 nm (typically between 150 and 200 nm). However, this must be largerthan the thickness of the channel-forming region. If its thickness issmaller than the thickness of the channel-forming region, the thicknessoffset region 304 could not exhibit good offsetting ability.

[0166] We, the present inventors refer to the structure of that typecomprising offset+LDD, as an HRD (high resistance drain) structure, anddifferentiate it from ordinary LDD structures. In this Embodiment, theHRD structure is a three-stage structure comprising maskoffset+thickness offset+LDD.

[0167] In this case, the LDD region 305 is controlled by its thicknessand the impurity concentration therein, and therefore has the advantageof high reproducibility and uniform characteristics. Contrary to this,the LDD region as formed by conventional patterning has the problem ofnon-uniform characteristics to be caused by the patterning error, as somentioned hereinabove with reference to the prior art.

[0168] As being controlled by the patterning, the length (X¹) of themask offset region 303 is influenced by the patterning error and even bythe glass shrinkage error. However, since the region 303 is followed bythe thickness offset region 304 and the LDD region 305, the influence ofthe error on the length of the region 303 is thereby reduced and thefluctuation in the characteristics of the region 303 may be reduced.

[0169] The length (X¹) of the mask offset region 303 may be representedby (C¹-L¹)/2 where L¹ indicates the channel length and C¹ indicates thelength of the channel-etching region. Accordingly, the intended offsetlength (X¹) can be defined in the patterning step of formingsource/drain electrodes. In the constitution of this Embodiment, theoffset length (X¹) may be from 0.3 to 3 _m (typically from 1 to 2 _m).

[0170] The inverse stagger-type TFT having the structure shown in FIG.2C could not be realized in any prior art of TFT having conventionalamorphous silicon films as the active layers (island semiconductorlayers). This is because, in the case of TFT comprising such anamorphous silicon film, if the source/drain electrodes are not soconstructed as to overlap with the gate electrode, the carrier (electronor hole) mobility is extremely low.

[0171] Even if the source/drain electrodes are so constructed as tooverlap with the gate electrode in TFT comprising an amorphous siliconfilm, the mobility (field effect mobility) of those TFT will be at mostfrom 1 to 10 cm² Vs or so. Contrary to this, if TFT comprising anamorphous silicon film are constructed like in the present Embodiment,their mobility is too low to function as switching devices.

[0172] As opposed to those conventional TFT, the TFT of the presentinvention comprises crystalline silicon films as the active layers, andthe carrier mobility therein is fully high. Therefore, the structure ofthis Embodiment ensures a satisfactorily high carrier mobility. In otherwords, using the semiconductor films having a crystalline structure asthe active layers realizes the TFT structure of this Embodiment.

[0173] Since the inverse stagger-type TFT of this Embodiment has the HRDstructure, it is highly resistant to hot carrier implantation to becaused by impact ionization, and therefore has high reliability. Inaddition, in the TFT of this Embodiment, the LDD region is formed in awell controlled manner and governs the other regions. Therefore, thecharacteristics of the TFT vary little.

[0174] Accordingly, the structure of this Embodiment is favorable to TFTcircuits that are required to have high voltage resistance but not soquick operating mobility.

[0175] As is known from the process of this Embodiment, only 4 masks areused to produce the inverse stagger-type TFT having the structure ofFIG. 2C. Considering the fact that conventional channel-stop-type TFTrequire 6 masks, the structure of this Embodiment means significantimprovements in the throughput and the yield of inverse stagger-typeTFT.

[0176] As in the above, using the structure of this Embodiment makes itpossible to produce bottom-gate-type TFT of high reliability and highproducibility on a mass-production scale.

[0177] The bottom-gate-type TFT (N-channel-type TFT) as producedaccording to the process of this Embodiment realize a mobility of from10 to 150 m² Vs (typically from 60 to 120 cm²/Vs) and a thresholdvoltage of from 1 to 4 V.

[0178] [Embodiment 2]

[0179] This is to demonstrate another embodiment of the invention, whichis different from Embodiment 1. The basic process of producing TFT inthis Embodiment 2 is the same as that in Embodiment 1. The differencesof Embodiment 2 from Embodiment 1 are described herein.

[0180] First prepared is the structure of FIG. 5A according to theprocess of Embodiment 1. The difference between the structure herein andthat in Embodiment 1 is that the length of the channel-etching region500 to be between the source electrode 501 and the drain electrode 502is C² herein. In this, C² is narrower than the width of the gateelectrode, and may fall between 2 and 9 _m (typically between 2 and 4_m). Specifically, this Embodiment is characterized in that the gateelectrode overlaps with the source/drain electrodes.

[0181] This structure of FIG. 5A is subjected to the channel-etchingstep as in Embodiment 1, and then coated with protective films. Thus isformed the structure of FIG. SB. In this, the region indicated by 503 isa channel-forming region, and the channel length is indicated by L²(=C²). By suitably designing the masks, the length (Y²) of theoverlapping regions (hereinafter referred to as mask-overlappingregions) is controlled to be (E−L²)/2 where E is the width of the gateelectrode.

[0182]FIG. 5C is an enlarged view of the drain region, in which thecarriers pass through the channel-forming region 503 (thickness: 50 nm),the mask-overlapping region 504 (thickness: 160 nm) and the LDD region505 (thickness: 50 nm) and reach the n⁺ layer 506 (thickness: 40 nm) andthe drain electrode 502, while the TFT is driven.

[0183] In this structure, the electric field from the gate electrodecovers the mask-overlapping region 504, but is attenuated toward the LDDregion 505. In this, therefore, the region 504 has substantially thesame function as that of the LDD region. Needless-to-say, the region 504nearest to the LDD region 505 is entirely free from the influence of theelectric field, and this functions also as an offset (thickness offset)region.

[0184] In this Embodiment, the HRD structure having the mask-overlappingregion is comprising overlapping substantial LDD+thicknessoffset+impurity-poor LDD. In the HRD structure in which themask-overlapping region 504 is thin, the LDD region may be comprisingoverlapping substantial LDD+impurity-poor LDD.

[0185] In the structure of this Embodiment, the overlapping region 504and the LDD region 505 each are well controlled to have a controlledthickness. Therefore, the characteristics of TFT having this structurevary little. The length (Y²) of each overlapping region may contain apatterning error. However, since the overlapping LDD, the thicknessoffset and the impurity-poor LDD are not influenced by the patterningerror, the length error of Y² has few negative influences on thecharacteristics of TFT.

[0186] The structure of this Embodiment has a reduced offset componentand is favorable to TFT circuits that are required to have quickoperating mobility.

[0187] Another advantage of the structure of this Embodiment is thatminor carriers having accumulated in the channel-forming region due toimpact ionization can rapidly move to the source electrode withoutcausing substrate floatation. Therefore, using the structure of thisEmbodiment realizes TFT that ensure quick operating motion and have highvoltage resistance.

[0188] [Embodiment 3]

[0189] This is to demonstrate still another embodiment of the invention,which is different from Embodiments 1 and 2. The basic process ofproducing TFT in this Embodiment 3 is the same as that in Embodiment 1.The differences of Embodiment 3 from Embodiment 1 are described herein.

[0190] First prepared is the structure of FIG. 6A according to theprocess of Embodiment 1. The difference between the structure herein andthat in Embodiment 1 is that the length of the channel-etching region600 to be between the source electrode 601 and the drain electrode 603is C³ herein. In this, C³ is the same as the width of the gateelectrode, and may fall between 1 and 10 _m (typically between 3 and 5_m).

[0191] This structure of FIG. 6A is subjected to the channel-etchingstep as in Embodiment 1, and then coated with protective films. Thus isformed the structure of FIG. 6B. In this, the region indicated by 603 isa channel-forming region, and the channel length is indicated by L³(=C³).

[0192]FIG. 6C is an enlarged view of the drain region, in which thecarriers pass through the channel-forming region 603 (thickness: 100nm), the thickness offset region 604 (thickness: 150 nm) and the LDDregion 605 (thickness: 100 nm) and reach the n⁺ layer 606 (thickness: 50nm) and the drain electrode 602, while the TFT is driven. In thisEmbodiment, the HRD structure has a two-stage structure of offset+LDD.

[0193] In the structure of this Embodiment, the thickness offset region604 and the LDD region 605 each are well controlled to have a controlledthickness. Therefore, the characteristics of TFT having this structurevary little. In addition, the voltage resistance of TFT having thisstructure is high.

[0194] [Embodiment 4]

[0195] This is to demonstrate still another embodiment of the invention,which is different from Embodiments 1 to 3. The basic process ofproducing TFT in this Embodiment 4 is the same as that in Embodiment 1.The differences of Embodiment 4 from Embodiment 1 are described herein.

[0196] First prepared is the structure of FIG. 7A according to theprocess of Embodiment 1. The difference between the structure herein andthat in Embodiment 1 is that any one of the source electrode 701 or thedrain electrode 702 overlaps with the gate electrode while the otherdoes not.

[0197] In this Embodiment, the length of the channel-etching region 700is C⁴, which may fall between 1 and 10 _m (typically between 3 and 6_m).

[0198] This structure of FIG. 7A is subjected to the channel-etchingstep as in Embodiment 1, and then coated with protective films. Thus isformed the structure of FIG. 7B. In this, the region indicated by 703 isa channel-forming region, and the channel length is indicated by L⁴ (=C⁴X⁴).

[0199] In this, X⁴ indicates the length of the mask offset region 704.For the numerical limitation of X⁴, referred to is Embodiment 1. For thenumerical limitation of the length of the mask-overlapping region 705,referred to is Embodiment 2.

[0200] The structure of this Embodiment comprises a combination of theHRD structure of Embodiment 1 and the HRD structure (or LDD structure)of Embodiment 2. For the details of the constituent structures herein,referred to are those in Embodiments 1 and 2.

[0201] In this Embodiment, it is desirable that the source region hasthe HRD structure (or LDD structure) of Embodiment 2 while the drainregion has the HRD structure of Embodiment 1.

[0202] The electric field concentration is great in the channel edge(junction) adjacent to the drain region. Therefore, for example, it isdesirable that the drain region in this Embodiment has the resistancecomponent-rich HRD structure as in Embodiment 1. On the contrary, thesource region in this Embodiment is not required to have such highvoltage resistance. To the source region herein, therefore, theresistance component-poor HRD (or LDD) structure as in Embodiment 2 isfavorable.

[0203] In this Embodiment, any one of the source/drain regions may becombined with the structure of Embodiment 2. In any manner, producersmay suitably select any of HRD and LDD structures such as thoseillustrated in Embodiments 1 to 3 to construct various types ofsource/drain regions and to design and produce optimum structures of TFTcircuits comprising the thus-constructed source/drain regions. In thatcase, various patterning of 3²=9 combinations is available.

[0204] [Embodiment 5]

[0205] This is to demonstrate the construction of a CMOS circuit(inverter circuit) comprising the bottom-gate-type TFT having theconstitution of any of Embodiments 1 to 4, with reference to FIG. 8. TheCMOS circuit is comprising N-channel-type TFT and P-channel-type TFT ascomplementarily formed and combined on one substrate.

[0206] The CMOS circuit illustrated in FIG. 8 comprises the structure ofEmbodiment 4, in which 801 is a source electrode for a P-channel-typeTFT, 802 is a source electrode for an N-channel-type TFT, and 803 is adrain electrode for both the N/P TFT.

[0207] The N-channel-type TFT comprises n+layers 804 and 805 and n⁻layers 806 and 807 all formed according to the process of Embodiment 1.On the other hand, the P-channel-type TFT comprises p⁺⁺ layers 808 and809 and p⁻ layers 810 and 811.

[0208] It is extremely easy to form the CMOS circuit on one substrate.In the case of the present invention, the structure of FIG. 2A is firstprepared according to the process of Embodiment 1.

[0209] Irrespective of N/P types, an element selected from Group 15 isadded to the entire surface of this structure. To produce theP-channel-type TFT in this structure, the region to be theN-channel-type TFT is masked with a resist mask or the like, and anelement selected from Group 13 (typically boron, indium or gallium) isadded to this.

[0210] In this Embodiment, boron is added to produce the P-channel-typeTFT. In this case, the dose of boron must be higher than the phosphorusconcentration by which the type of the conductivity of the intendedregion is inverted. In order to completely convert all the n⁺ layer andthe n⁻ layer to the p⁺⁺ layer and the p⁻ layer, the concentrationprofile in boron addition must be so controlled that the boron depth islarger than the phosphorus depth.

[0211] Accordingly, the boron concentration profile in the film is as inFIG. 9. In FIG. 9, 900 is a semiconductor film, 901 is a phosphorusconcentration profile prior to boron addition, 902 is a boronconcentration profile after boron addition, 903 is a p⁺⁺ layer, 904 is ap⁻ layer, and 905 is an i-layer.

[0212] In this case, the p⁺⁺ layer has a thickness of from 10 to 150 nm(typically from 50 to 100 nm), and the boron concentration in the p⁺⁺layer is so controlled that it falls between 3×10¹⁹ and 1×10²²atoms/cm³, but typically between 3×10¹⁹ and 3×20²¹ atoms/cm³.

[0213] On the other hand, the p⁻ layer has a thickness of from 30 to 300nm (typically from 100 to 200 nm), and the boron concentration in the p⁻layer is so controlled that it falls between 5×10¹⁷ and 3×10¹⁹atoms/cm³. However, since the P-channel-type TFT naturally has highdurability, the formation of the p⁻ layer for the LDD region is notalways necessary. The reason why the thickness of the p⁻ layer 904 isspecifically referred to herein is because the p⁻ layer is all the timeformed in the ion implantation for boron addition that brings about thecontinuously varying boron concentration profile.

[0214] In this Embodiment, both the N-channel-type TFT and theP-channel-type TFT have the HRD structure (comprising overlappingregions) of Embodiment 2 in their source regions, while having the HRDstructure (comprising mask offset regions) of Embodiment 1 in theirdrain regions.

[0215] Accordingly, as will be obvious from the top view of FIG. 8, thesource region in the P-channel-type TFT has an overlapping region havinga length of Yi, while the drain region therein has a mask offset regionhaving a length of Xi. On the other hand, the source region in theN-channel-type TFT has an overlapping region having a length of Yj,while the drain region therein has a mask offset region having a lengthof Xj.

[0216] In this case, the lengths of Xi, Xj, Yi and Yj can freely bevaried depending on mask designing. Accordingly, each length of thosemay be suitably determined in accordance with the necessity for thecircuit constitution, and it is not always necessary to unify thelengths in the N-channel-type and P-channel-type TFT.

[0217] In the CMOS circuit having the structure illustrated herein, thevoltage resistance of the region to be the common drain is high.Therefore, the structure of the illustrated type is extremely useful inconstructing circuits for high operating voltage.

[0218]FIG. 8 shows the constitution of the CMOS circuit comprising TFTof Embodiments 1 to 4. Needless-to-say, however, any other combinationsexcept the illustrated constitution are acceptable. Nine combinationsare available for one TFT. Therefore, 9²=81 modifications or variationsare acceptable for patterning constitution of one CMOS circuit. Fromthose plural combinations. the optimum ones may be selected and employedin accordance with the necessary properties of the circuits to beproduced.

[0219] As has been illustrated in this Embodiment, the present inventionis easily applicable to P-channel-type TFT. In that case, thebottom-gate-type TFT (P-channel-type TFT) of the invention realize amobility of from 10 to 100 cm²/Vs (typically from 50 to 100 cm²/Vs) anda threshold voltage of from −1.5 to −5 V.

[0220] [Embodiment 6]

[0221] This is to demonstrate one embodiment of the means of controllingthe threshold voltage of TFT of the invention.

[0222] For threshold voltage control, an element selected from Group 13(typically boron, indium, gallium) or Group 15 (typically phosphorus,arsenic, antimony) may be added to a channel-forming region. Thistechnique is referred to as channel doping.

[0223] The technique of channel doping is effective in the presentinvention, for which any of the following two methods is preferred asbeing simple.

[0224] The first method comprises adding a gas that contains an impurityfor threshold voltage control (e.g., diborane, phosphine, etc.) to thefilm forming gas for the amorphous silicon film. In this method, theformed film contains a predetermined amount of the impurity. This methoddoes not require any additional step for impurity addition. However, inthis method, both the N-type and P-type TFT have the same impurityconcentration. Therefore, this method is not available for the casewhere the N-type and P-type TFT have a different impurity concentration.

[0225] The second method comprises adding an impurity selectively to thechannel-forming region (or to the channel-forming region and the maskoffset region) via the source/drain electrodes acting as masks, afterthe channel-etching step (for forming the channel-forming region) as inFIG. 2C.

[0226] For this, available is any of ion implantation, ion doping,plasma processing, gaseous phase addition (for impurity diffusion fromgaseous atmosphere), solid phase addition (for impurity diffusion fromsolid film) and the like. Since the channel-forming region is thin,gaseous phase addition, solid phase addition and the like that cause nodamage to the region are preferred.

[0227] In ion implantation, it is desirable to cover the entire surfaceof TFT with a protective film, by which the channel-forming region isprotected from being damaged.

[0228] After the impurity has been added to the film, it is activatedthrough laser annealing, lamp annealing, furnace annealing or theircombination. In this step, the damage of the channel-forming region isalmost completely recovered.

[0229] In this Embodiment, the concentration of the impurity forthreshold voltage control, which is added to the channel-forming region,may fall between 1×10¹⁵ and 5×10¹⁸ atoms/cm³ (typically between 1×10¹⁵and 5×10¹⁷ atoms/cm³).

[0230] The threshold voltage of the N-channel-type TFT of the invention,to which the embodiment of this Embodiment has been applied, may fallbetween 1.5 and 3.5 V. The threshold voltage of the P-channel-type TFTof the invention, to which the same has been applied, may fall between−1.5 and −3.5 V.

[0231] The constitution of this Embodiment may be combined with anyconstitution of Embodiments 1 to 5. Where it is combined with the CMOScircuit of Embodiment 5, the type of the impurity and even theconcentration thereof may be changed in the N-type TFT and the P-typeTFT.

[0232] [Embodiment 7]

[0233] The structure of FIG. 2C has the source electrode 112 and thedrain electrode 113 that entirely surround the island semiconductorlayer. This Embodiment is to demonstrate a structure partly differentfrom the structure of FIG. 2C.

[0234] Referred to is the structure of FIG. 10A, which is basically thesame as the structure of FIG. 2C but is partly different from it. Thestructure of FIG. 10A is characterized in that the shape of the sourceelectrode 11 and that of the drain electrode 12 differ from those inFIG. 2C. Specifically, in the structure of FIG. 10A, the sourceelectrode 11 and the drain electrode 12 are formed partly inside theisland semiconductor layer (strictly, inside the source/drain regions)by the distance of “a”.

[0235] The region indicated by 13 has a thickness that is the same asthe thickness of the channel-forming region 14, and has a width that isthe same as the distance of “a”. Though graphically shown in thedrawing, the distance “a” is from 1 to 300 _m (typically from 10 to 200_m).

[0236] The characteristics of this Embodiment will be mentioned below,with reference to the process of producing the structure of thisEmbodiment. As in FIG. 10B, the source electrode 11 and the drainelectrode 12 are formed herein. In this, the edges 16 of an islandsemiconductor layer 15 are exposed outside.

[0237] The structure of FIG. 10B is subjected to a channel-etching step,where the island semiconductor layer 15 is self-alignedly etched via thesource electrode 11 and the drain electrode 12 both acting as masks. Inthis, the edges 16 are also etched.

[0238] As a result of the etching, obtained is the structure of FIG.10A. In the thus-obtained structure, it is obvious that the thickness ofthe edges 16 is the same as that of the channel-forming region 14.

[0239] In this Embodiment, the protrusions 13 of the islandsemiconductor layer are formed for the following two reasons.

[0240] These are used for etching monitoring in the channel-etchingstep.

[0241] In the subsequent steps of forming a protective film and aninterlayer insulating film, these protrusions are effective for reducingthe coverage failure to be caused by the height of the islandsemiconductor layer.

[0242] For the etching monitoring, the products being produced aresampled and the samplings are inspected at their protrusions to checkthe etching degree at the channel-forming region.

[0243] The structure of this Embodiment may be combined with anystructure of Embodiments 1 to 6.

[0244] [Embodiment 8]

[0245] This is to demonstrate one embodiment of the circuit constitutionof the CMOS circuit (inverter circuit) of Embodiment 5, with referenceto FIG. 11A to FIG. 11C.

[0246]FIG. 11A shows a CMOS circuit of which the structure is the sameas that in FIG. 8. The CMOS circuit illustrated comprises a gateelectrode 20, an N-type TFT semiconductor layer 21, a P-type TFTsemiconductor layer 22, an N-type TFT source electrode 23, a P-type TFTsource electrode 24 and a common drain electrode 25.

[0247] The terminals, a, b, c and d correspond to those of a, b, c andd, respectively, of the inverter circuit shown in FIG. 11 C.

[0248]FIG. 11B shows a modification of the CMOS circuit, in one and thesame semiconductor layer of the drain region is formed for both theN-type TFT and the P-type TFT. The numeral and code references in FIG.11B correspond to those in FIG. 11A.

[0249] In the structure of FIG. 11B, all TFT can be formed at anextremely high density. Therefore, this structure is extremely effectivein producing large-scale integration circuits. In this, the commonsemiconductor layer will form PN junctions, which, however, produce noproblem.

[0250] [Embodiment 9]

[0251] In Embodiment 1, the amorphous semiconductor film is crystallizedwith laser beams, especially with pulse-oscillation excimer laser beamsfor fusion crystallization. In this, laser beams or intense light ofwhich the intensity is equivalent to laser beams can be used forcrystallizing the amorphous semiconductor film through solid phasecrystal growth, without distorting the glass substrate.

[0252] As the light source for generating such intense light or laserbeams, usable is any of IR lamps such as halogen lamps, or continuousoscillation lasers such as Ar lasers. RTA (rapid thermal annealing) forwhich are used IR lamps or continuous oscillation lasers ensurescrystallization of amorphous semiconductor films under heat for a fewseconds to tens seconds, and therefore realizes great improvements inthroughput.

[0253] Where amorphous semiconductor (e.g., silicon) films are exposedto light from IR lamps or to continuous oscillation laser beams, thelight absorbed by the films is converted into heat, and thethus-generated heat acts on the films to form crystal nuclei therein. Inthose films, the nuclei grow in the solid phase, resulting in that thefilms are converted into crystalline semiconductor films.

[0254] Where a halogen lamp (peak wavelength: 1.15 _m, wavelength range:0.4 to 4 _m) is used, the heating time may fall between 10 and 60seconds, but typically between 15 and 30 seconds. With this, amorphoussemiconductor films are heated at 700 to 1000_C. In this case, eventhrough the films are heated at 700 to 1000_C, the underlying glasssubstrate is not heated over its distortion point (650 to 700_C or so),since the glass substrate hardly absorbs IR rays and since the exposuretime is short.

[0255] After amorphous semiconductor films have been crystallized withIR lamps or continuous oscillation laser beams, it is desirable that theresulting crystalline semiconductor films are further exposed to laserbeams for annealing to thereby increase the degree of crystallinity ofthe films. In this case, the annealing with laser beams may be performedfor activating the impurity added to the films.

[0256] The RTA technique of this Embodiment for crystallizingsemiconductor films may be combined with all other Embodimentsillustrated herein.

[0257] [Embodiment 10]

[0258] This is to demonstrate the production of an active-matrix-typedisplay device that comprises a driver circuit (peripheries-drivingcircuit) and a pixel matrix circuit as integrated on one substrate, withreference to the basic process of Embodiment 1.

[0259] In this Embodiment, the basic constitution of the driver circuitcomprises a CMOS circuit (of the type illustrated in FIG. 11B). Apartfrom the driver circuit, the other information processing circuits ofD/A converter circuit, memory circuit,-co rrection circuit and others(these are differentiated from the driver circuit and will be referredto as logic circuits) may also comprise TFT of the invention. For thoselogic circuits, a CMOS circuit is the base circuit.

[0260] A multi-gate TFT is usable as the pixel matrix circuit. In thisEmbodiment, used is a double-gate structure for the pixel matrixcircuit, which, however, is not limitative. Apart from this, any of asingle-gate structure or a triple-gate structure is available.

[0261] According to the process of Embodiment 1, an amorphous siliconfilm was crystallized through laser irradiation to form the structure ofFIG. 1B. This is in FIG. 12A.

[0262] In FIG. 12A, 30 is a glass substrate, 31 is a undercoating film,32 is a PTFT gate electrode to be a CMOS circuit, and 33 is an NTFT gateelectrode. In this, 34 and 35 are pixel TFT gate electrodes, and theseare connected with each other in the site not shown in the drawing. Asthe material for the gate electrodes 32 to 35, used is an aluminum film(containing 2 wt. % Sc). To protect the gate electrodes from beingthermally and physically damaged, aluminum oxide films 3000 and 3001 areformed through anodic oxidation around the gate electrodes 32 and 33 ofthe CMOS circuit, and the pixel TFT gate electrodes 34 and 35 are alsocoated with an aluminum oxide film 3002 as formed through anodicoxidation. The oxide films 3001 to 3002 are formed in the same manner asin Embodiment 1.

[0263] As the material for the gate electrodes, also available is any ofmetallic suicides and other metals of titanium, chromium or the like, inplace of aluminum. For example, as a conductive film capable of beingsubjected to anodic oxidation, available is any of a laminate filmcomprising tantalum (Ta) and tantalum nitride (TaN), or a simplesubstance film of tantalum. On the surface of the electrodes of thattype, an oxide film of Ta²O⁵ may be formed through anodic oxidation. Ashaving higher heat resistance than an aluminum film, the laminate filmof tantalum (Ta) and tantalum nitride (TaN) may be directly processedaccording to the process of the invention without forming an oxide filmthereover through anodic oxidation.

[0264] Over the oxide films 3000 to 3002, formed are a silicon nitridefilm 36 and a silicon oxynitride film 37. In place of the siliconoxynitride film 37, a silicon oxide film may be formed. In the pixel TFTand the CMOS circuit, the laminate of the silicon nitride film 36 andthe silicon oxynitride film 37 as formed over the oxide films 3000 to3002 functions as a gate-insulating layer.

[0265] Over the silicon oxynitride film 37, formed is a crystallinesilicon film 3003 through laser crystallization as in Embodiment 1.

[0266] Next, phosphorus is added to the structure of FIG. 12A, in whichare formed an n⁺ layer 38, an n⁻ layer 39 and an i-layer 40 in thecrystalline silicon film 3003, as in FIG. 12B. For the details of theselayers, referred to is the description of Embodiment 1.

[0267] Next, boron, which is an element selected from Group 13, is addedto the region to be the PTFT of the CMOS circuit through ionimplantation or ion doping, while the area except this region is maskedwith a resist mask (not shown). In this Embodiment, the boron dose isthree times the phosphorus dose in the previous step, by which areformed a p⁺⁺ layer 41 and a p⁻ layer 42. In this step, the type of theion to be doped and the accelerated voltage for the ion doping must beso controlled that an intrinsic or substantially intrinsic i-layer 40may remain below the p⁻ layer 42. For the details of the p⁺⁺ layer 41and the p⁻ layer 42, referred to is the description of Embodiment 5.(FIG. 12C)

[0268] Next, this is annealed with laser beams, by which thecrystallinity of the crystalline silicon film 3003 having become partlyamorphous due to the addition of phosphorus and boron thereto isimproved. The laser annealing activates the impurities (phosphorus andboron) in the film 3003. Prior to this laser annealing, the film 3003may be dehydrogenated through RTA to thereby prevent hydrogen bumping inthe laser annealing step. (FIG. 12D)

[0269] Next, the crystalline silicon film 3003 is etched to form islandsemiconductor layers 43 and 44. In this step, contact holes are formedthrough the film 3003, through which a part of the gate wiring isconnected with the electrodes to be formed in the next step (secondwiring).

[0270] The laser annealing may be performed after the formation of theisland semiconductor layers 43 and 44 of the crystalline silicon film.

[0271] Next, a thin conductive film is formed over the layers 43 and 44,and patterned to form source electrodes 45 (NTFT) and 46 (PTFT) and acommon drain electrode 47 for the CMOS circuit. In the same manner, asource electrode 48 and a drain electrode 49 for the pixel TFT areinformed. The electrode indicated by 50 functions only as a mask, andthis is referred to as a mask electrode herein. (FIG. 13A)

[0272] The structure of FIG. 13A thus constructed is etched to formchannel-forming regions 51 to 54. In this case, the driver circuit is soconstructed that mask offset regions are formed adjacent to the drainregions only of the both TFT, while overlapping regions are formedadjacent to the both source regions.

[0273] In this, the pixel TFT is so constructed that mask offset regionsare formed adjacent to the source electrode 48 and to the drainelectrode 49, while an overlapping region is formed below the maskelectrode 50.

[0274] In the pixel TFT, the source/drain regions are switched duringcharging and discharging for image information inputting. Therefore, theboth edges of the TFT must have high voltage resistance. In thisstructure, if the concentration of the resistance components is too highin the area below the mask electrode 50, the switching motion of thedevice will be retarded. In order to evade this problem, it is desirablethat an overlapping region is provided in this area to therebyfacilitate the carrier movement therethrough.

[0275] This Embodiment is to demonstrate one embodiment which isconsidered to be the most preferred one, and is not limited to only thestructure illustrated herein. Producers may select the optimum structurein combination with any of the structures of Embodiments 1 to 4, whiletaking the advantages of the structures of Embodiments 1 to 4 intoconsideration.

[0276] Next, a protective film 55 of a silicon oxynitride film having athickness of 200 nm is formed over the structure of FIG. 13B, and thisis further coated with an interlayer insulating film of an organic resinfilm. To form the organic resin film 56, available is any of polyimide,polyamide, polyimidamide or acrylic resin.

[0277] Next, a contact hole is formed through the interlayer insulatingfilm 56, into which is formed a pixel electrode 57 of a transparentconductive film (typically ITO). Finally, this is hydrogenated tocomplete an active matrix substrate, as in FIG. 13C.

[0278] Next, a liquid crystal layer is put between the active matrixsubstrate produced herein and a counter substrate, according to a knowncell-constructing method, to produce an active-matrix-type liquidcrystal display device.

[0279] To produce the active matrix substrate of this Embodiment, sevenpatterning steps are necessary, which are as follows:

[0280] Gate electrode patterning.

[0281] boron-doped region patterning.

[0282] island semiconductor layer patterning.

[0283] Gate contact patterning.

[0284] Source/drain electrodes patterning.

[0285] ITO contact patterning.

[0286] ITO patterning.

[0287] As above, producing the active matrix substrate requires only asmall number of masks. Therefore, the throughput of the display devicecomprising the substrate is greatly increased. In addition, any desiredcircuits can be freely designed and formed on the substrate while usingthe TFT of Embodiments 1 to 5. Therefore, according to the technique ofthis Embodiment, display devices of high reliability and highreproducibility are easy to realize.

[0288]FIG. 14A shows a top view of a part of the pixel matrix circuit ofthis Embodiment, in which the reference numerals have the same meaningsas above. The part of this drawing not referred to hereinabove isdescribed below.

[0289] A cross-sectional view of FIG. 14A as cut along the line A-A′ isshown in FIG. 14B. Though not shown in FIG. 13C, a capacity wiring 58 ofan aluminum film, which is the same as that for the gate wiring, isformed in parallel to the gate wiring, as in FIG. 14B. The surface ofthe capacity wiring 58 is subjected to anodic oxidation to have an oxidefilm 3005 thereon.

[0290] The capacity wiring 58 provides a subsidiary capacitance (Cs) inthe region 1401 that overlaps with the drain electrode 50 (the region1401 is surrounded by the dotted line in the drawing). In this case, thegate-insulating layers 3005, 36 and 37 are the dielectrics for thesubsidiary capacitance. The constitution of the subsidiary capacitanceis not limited to only the embodiment illustrated in this Embodiment.

[0291] [Embodiment 11]

[0292] Embodiment 10 is to demonstrate an embodiment of using asemiconductor film as crystallized through laser irradiation to form adriver circuit (peripheries-driving circuit) and a pixel matrix circuitas integrated on one substrate. Being different from that, thisEmbodiment is to demonstrate an embodiment of crystallizing asemiconductor film through RTA.

[0293]FIG. 15A to FIG. 15D show a process of the embodiment of thisEmbodiment. In those drawings, the numeral references have the samemeanings as those in FIG. 12A to FIG. 12D. An amorphous silicon filmhaving a thickness of from 100 to 600 nm is formed on a siliconoxynitricle film 37. In this Embodiment, the thickness of the amorphoussilicon film is 200 nm. Next, the amorphous silicon film is crystallizedthrough RTA for solid phase crystal growth, as in Embodiment 9, toconvert it into a crystalline silicon film 3004.

[0294] In the crystallization step of this Embodiment, used is a halogenlamp (peak wavelength: 1.15 _m, wavelength range: 0.4 to 4 _m). Thelight from the lamp is linearly focused to give a linear beam having awidth of 10 mm, and scanned over the substrate. Depending on thescanning rate, the exposure time was controlled to fall between 10 and60 seconds but typically between 15 and 30 seconds. By controlling theoutput of the halogen lamp, the amorphous silicon film is heated at 700to 1000_C. In this Embodiment, the scanning rate is 0.5 mm/sec (thiscorresponds to an exposure time of 20 seconds), the output of thehalogen lamp is 7.7 W, and the amorphous silicon film is thus heated atabout 920_C to be crystallized into the crystalline silicon film 3004.

[0295] After the crystallization through RTA, the crystalline siliconfilm 3004 is annealed by exposing it to laser beams of excimer laser,YAG laser or the like or to intense light equivalent to such laserbeams. The annealing is to additionally crystallize the amorphouscomponent still remaining in the crystalline silicon film 3004 tothereby enhance the crystallinity of the film 3004.

[0296] Solid phase crystallization in an electric furnace takes tenshours, but RTA crystallization takes only tens seconds. Therefore, thelatter is advantageous in that the throughput of the devices produced ishigh and that the thermal damage to glass substrates is small.

[0297] After the RTA crystallization, the crystalline silicon film 3004is processed in the same manner as in Embodiment 10. Briefly, as in FIG.15B, phosphorus is added to the film 3004 to form an n⁺ layer 38, an n⁻layer 39, and an i-layer 40. Next, boron is added thereto to form a p⁺⁺layer 41 and a p⁻ layer 42, as in FIG. 15C.

[0298] Next, this is annealed with laser beams, as in FIG. 15D, by whichthe crystallinity of the crystalline silicon film 3004 having becomepartly amorphous due to the addition of phosphorus and boron thereto isimproved. The laser annealing activates the impurities (phosphorus andboron) in the film 3004. Prior to this laser annealing, the film 3004may be dehydrogenated through RTA to thereby prevent hydrogen bumping inthe laser annealing step.

[0299] Next, the structure of FIG. 15D is processed according to theprocess of Embodiment 10 illustrated in FIG. 13A to FIG. 13C and FIG.14A and FIG. 14B, whereby is formed an active-matrix-type display devicehaving a driver circuit and a pixel matrix circuit as integrated on thesubstrate.

[0300] [Embodiment 12]

[0301] This Embodiment is to demonstrate still another embodiment ofproducing an active-matrix-type display device, which is different fromthe embodiments of Embodiments 10 and 11.

[0302] The process of this Embodiment is characterized in that thefusion crystallization with laser beams or the solid phasecrystallization through RTA is not followed by laser annealing forimproving the crystallinity of the crystalline film formed. In otherwords, in this Embodiment, the crystalline film formed is directlysubjected to the next step of adding phosphorus to the film. In this,the phosphorus addition may be performed in the same manner as inEmbodiment 10.

[0303] Specifically, the process of this Embodiment is characterized inthat the crystallinity of the channel-forming region is improved (inthis step, the impurities added are activated, and the film isrecrystallized) after a protective film 55 is formed as in FIG. 16. Inthis process, the channel-forming regions 51 to 54 are self-alignedlyexposed to laser beams via the protective film 55 of a siliconoxynitride film.

[0304] The laser annealing of the structure of FIG. 16 is advantageousin that it prevents out-diffusion of impurities of phosphorus and boronfrom the source/drain regions and that the power of the laser beams(laser energy) necessary for it may be reduced to a half or so.

[0305] This Embodiment is not limited to only the structure illustratedin the drawings. Producers may select the optimum structure incombination with any of the TFT structures of Embodiments 1 to 4, whiletaking the advantages of those structures of Embodiments 1 to 4 intoconsideration, for designing the intended circuits. This Embodiment maybe combined with any structures of all other Embodiments.

[0306] [Embodiment 13]

[0307] This Embodiment is to demonstrate still another embodiment ofproducing an active-matrix-type display device, in which the laserannealing step just after the crystallization step in the processes ofEmbodiments 10 and 11 is omitted, like in Embodiment 12. In thisEmbodiment, the crystallization step is followed by ion doping foradding phosphorus to the crystalline silicon film to form the n⁺ layer38 and the n⁻ layer 39 (see FIG. 12B, FIG. 15B). Next, boron is addedthereto also through ion doping to form the p⁺⁺ layer 41 and the p⁻layer 42 for PTFT in the semiconductor layer (see FIG. 12C, FIG. 15C).

[0308] The structure thus produced is subjected to RTA. In thisEmbodiment, this RTA treatment is to active the impurities added(phosphorus and boron) and to dehydrogenate the semiconductor layer(since hydrogen ions are implanted into the layer along with phosphorusand boron ions in the ion doping not followed by mass separation). (FIG.17A)

[0309] Next, this is annealed with laser beams. In this step, thesemiconductor layer having become amorphous in the previous steps ofadding the impurities is recrystallized to improve the crystallinity ofthe layer. If desired, this laser annealing step may be performed afterthe semiconductor layer is etched to give an island semiconductor layer.

[0310] After this, the structure is processed in the same manner as inEmbodiment 10. This Embodiment is not limited to only the structureillustrated in the drawings. Producers may select the optimum structurein combination with any of the TFT structures of Embodiments 1 to 4,while talking the advantages of those structures of Embodiments 1 to 4into consideration, for designing the intended circuits. This Embodimentmay be combined with any structures of all other Embodiments.

[0311] [Embodiment 14]

[0312] This Embodiment is to demonstrate the production of areflection-type liquid crystal display device, based on the process ofEmbodiment 10. FIG. 18A shows a top view of one pixel of a pixel matrixcircuit of a reflection-type liquid crystal display device.

[0313] In FIG. 18A, the parts corresponds to those in Embodiment 10 aredesignated by the same numerals as in Embodiment 10, and the detaileddescription of the parts is omitted herein. FIG. 18B is across-sectional view of FIG. 18A as cut along the line B-B′.

[0314] The difference between Embodiment 14 and Embodiment 10 is thatthe capacity wiring 59 covers the entire area of the pixel in theformer. Being different from the transmittance-type device of Embodiment10, the reflection-type device of this Embodiment 14 is not required tohave a large aperture. Therefore, in this, the back surface of the pixelelectrode 61 could be everywhere in service.

[0315] In this Embodiment, the drain electrode 60 is so positioned thatit covers the entire area of the pixel and overlaps with the capacitywiring 59 in a largest possible range. In that manner, almost all areaof the pixel can be utilized as the subsidiary capacitance, whereby thedevice may have a large capacity. The dielectrics for the subsidiarycapacitance are the oxide film 3005 formed through anodic oxidation, thesilicon nitride film 36 and the silicon oxynitride film 37.

[0316] The pixel electrode 61 is a reflective electrode, and it isdesirable that the electrode is made from aluminum having highreflectivity or from a material comprising mainly aluminum. Where theliquid crystal display device of this Embodiment is used inprojection-type displays, it is desirable that the pixel electrode has aflat and smooth surface. On the other hand, where it is used in directviewing displays, the surface of the pixel electrode must be roughenedto make it have an increased irregular reflectivity and have a broadenedangle of visibility.

[0317] This Embodiment is not limited to only the structure illustratedin the drawings. Producers may select the optimum structure incombination with any of the TFT structures of Embodiments 1 to 4, whiletaking the advantages of those structures of Embodiments 1 to 4 intoconsideration, for designing the intended circuits. This Embodiment maybe combined with any structures of all other Embodiments.

[0318] [Embodiment 15]

[0319] This Embodiment is to demonstrate a modification of the liquidcrystal display device of Embodiment 10. Herein formed are BM (blackmatrices) in the device.

[0320] According to the process of Embodiment 10, a layered structurehaving an interlayer insulating film 56 is formed. In this Embodiment,the interlayer insulating film 56 is made of a photosensitive acrylicresin. The interlayer insulating film 56 is patterned, and half-etchedto form depressions 65 and 66. (FIG. 19A)

[0321] The entire surface of the structure of FIG. 19A is coated with ablack resin film (not shown). The black resin film is an organic resinfilm containing graphite, carbon, dye or the like. The organic resinfilm may be a film of polyimide, acrylic resin or the like. In thisEmbodiment, used is a photosensitive acrylic resin containing graphiteas dispersed therein.

[0322] After thus coated with the black resin film, the region of thedepressions 65 and 66 only is selectively exposed, whereby the blackresin film remains only in that region. Next, this may be ashed in anoxygen plasma atmosphere to thereby increase the surface smoothness ofthe black resin films remained.

[0323] In that manner, formed are black matrices 67 and 68 of the blackresin. Next is formed a pixel electrode 69 of an ITO film. In thisEmbodiment, the pixel electrode 69 is so patterned that the edge of thepixel electrode 69 overlaps with the edge of the black matrix 68 (thatis, the edge of the pixel electrode 69 is inside the BM, black matrix68, as so indicated by 70).

[0324] As in the above, completed is an active matrix substrate havingthe structure of FIG. 19B. This is used in ordinary cell construction toproduce liquid crystal display devices. The black matrices produced inthis Embodiment have the advantage of not producing parasiticcapacitance with other wiring parts.

[0325] This Embodiment is not limited to only the structure illustratedin the drawings. Producers may select the optimum structure incombination with any of the TFT structures of Embodiments 1 to 4, whiletaking the advantages of those structures of Embodiments 1 to 4 intoconsideration, for designing the intended circuits. This Embodiment maybe combined with any structures of all other Embodiments.

[0326] [Embodiment 16]

[0327] This is to demonstrate a modification of Embodiment 15, withreference to FIG. 20 and FIG. 21. The black matrices formed herein aredifferent from those in Embodiment 15. Concretely, a conductive film isused to form the black matrices herein.

[0328] In FIG. 20, 56 is an interlayer insulating film of an organicresin film, and 71 to 74 are black matrices or wiring patterns actingalso as black matrices, which are made of a conductive film. Theconductive film may be any of titanium film, chromium film,titanium/aluminum laminate film or the like.

[0329] As being conductive, the black matrices in this Embodiment havevarious additional functions. The pattern 71 is a black matrix as fixedto the common voltage (earth voltage). The pattern 72 is connected withthe drain electrode of a CMOS circuit, and is used as a lead wire. Inthat manner, this Embodiment easily realizes a multi-layered wiringstructure.

[0330] The pattern 73 is connected with the source electrode of the CMOScircuit, and functions as a connection wire and also as a black matrix.The pattern 74 is a black matrix as positioned in the pixel matrixcircuit, and this is basically provided over the other wiring patternsand TFT.

[0331] Over the black matrices (or wiring patterns also acting as blackmatrices) 71 to 74, further provided is an interlayer insulating film75. The interlayer insulating film 75 may be made of a silicon oxidefilm, a silicon nitride film, a silicon oxynitride film, an organicresin film or a laminate of those films. The interlayer insulating film75 functions later as the dielectric for subsidiary capacitance.

[0332] Through the interlayer insulating film 75, formed is a contacthole, in which is formed a pixel electrode 76 of ITO. In the pixelmatrix circuit, the black matrix 74 and the pixel electrode 76 producesubsidiary capacitance 77.

[0333]FIG. 21 shows one embodiment of the positioning of black matricesin the pixel matrix circuit. In the embodiment of FIG. 21, a blackmatrix 78 is positioned to overlap with the structure of FIG. 14A. InFIG. 21, the thick line 79 is a pixel electrode, and 80 is a contactpart at which the pixel electrode 79 is contacted with the underlyingdrain electrode.

[0334] The black matrix 78 basically covers the other wiring patternsand TFT, while having opening windows only in the image-displayingregion 81 and the contact part 80. For transmission-type liquid crystaldisplay devices such as that illustrated in this Embodiment, the mostimportant matter is to reduce the area that is occupied by the blackmatrices to thereby broaden the area of the image-displaying region 81(that is, to increase the aperture of the device).

[0335] This Embodiment is not limited to only the structure illustratedin the drawings. Producers may select the optimum structure incombination with any of the TFT structures of Embodiments 1 to 4, whiletaking the advantages of those structures of Embodiments 1 to 4 intoconsideration, for designing the intended circuits. This Embodiment maybe combined with any structures of all other Embodiments.

[0336] [Embodiment 17]

[0337] This is to demonstrate still another embodiment of producing anactive matrix substrate, in which the TFT structure differs from thatillustrated in Embodiment 10. Herein referred to is FIG. 22.

[0338] The most important point in the structure of FIG. 22 is that theuppermost part of each semiconductor layer (in source/drain regions) isa first conductive layer (n⁺ region or p⁺⁺ region), and that eachconductive layer is covered with a protective film 55 and an interlayerinsulating film 56, and is electrically connected with lead electrodes81 to 85.

[0339] To produce the illustrated structure, channel etching to give thechannel-forming regions is performed via resist masks. After the channeletching in that manner, the protective film 55 and the interlayerinsulating film 56 are formed over the conductive layers, and thereafterthe lead electrodes 81 to 85 are formed.

[0340] In the structure of this Embodiment, the lead electrodes (thesefunction as source/drain electrodes or as rounding wires) 81 to 85 arespaced from the gate electrode by the interlayer insulating film 56.Accordingly, in this structure, the parasitic capacitance between thesource/drain electrodes and the gate electrode can be much more reduced.More effectively, the interlayer insulating film 56 is made from anorganic resin material having a small dielectric constant.

[0341] The structure of this Embodiment is applicable to TFT ofEmbodiments 1 to 4. Needless-to-say, it can be combined with anystructures of all other Embodiments. This Embodiment is not limited toonly the structure illustrated in the drawings. Producers may select theoptimum structure in combination with any of the TFT structures ofEmbodiments 1 to 4, while taking the advantages of those structures ofEmbodiments 1 to 4 into consideration, for designing the intendedcircuits.

[0342] [Embodiment 18]

[0343] This is to demonstrate one embodiment of connecting the activematrix substrate of any of Embodiments 10 to 18 with external terminals,with reference to FIG. 23. FIG. 23 is an enlarged view of a connectingsite at which the active matrix substrate is connected with an externalterminal (typically, flexible print circuit, FPC). The connecting siteis referred to as an FPC connecting site, and this is positioned at theedge of the active matrix substrate.

[0344] In FIG. 23, 101 is a glass substrate, and 86 is an insulatinglayer. The insulating layer 86 has a laminate structure comprising theundercoating film 102, the silicon nitride film 104 and the siliconoxynitride film 105 all shown in FIG. 1(A). A second wiring layer 87 isformed over the substrate 101 and the layer 86. The second wiring layer87 is a connecting wire layer via which the information from theexternal terminal is transmitted to the source/drain electrodes, thegate electrode, etc.

[0345] This Embodiment is characterized in that the second wiring layer87 is in direct contact with the glass substrate 101. To realize thisstructure, the insulating layer 86 below the FPC connecting site must becompletely removed in the third patterning step in the process ofEmbodiment 1. In this structure, the second wiring layer 87 is directlyformed on the hard glass substrate. Therefore, in this, FPC is firmlyfixed to the second wiring layer 87 in the FPC connecting site.

[0346] In the FPC connecting site, the interlayer insulating film 56 ispartially removed in the subsequent step, whereby the overlying ITO film57 is directly contacted with the second wiring layer 87. In thisstructure, the ITO film 57 is so laminated over the second wiring layer87 that it is directly contacted with at least the second wiring layer87 in the FPO connecting site. As the case may be, an independentpattern of an electrode pad of the ITO film 57 may be formed only in theFPC connecting site.

[0347] The ITO film 57 functions as a buffer layer for anisotropicconductive films 88 to be formed in the subsequent step. The anisotropicconductive films 88 contain conductive particles (of gold-coated silicaglass or the like), and the conductive particles are pushed into the ITOfilm to improve the ohmic contact between the FPC terminal 89 and theITO film 57.

[0348] At the FPC connecting site having the constitution shown in FIG.23, the FPC terminal 89 is pressed against the active matrix substratevia the anisotropic conductive films 88 formed therebetween. In thatmanner, the external terminal, FPC is connected with the active matrixsubstrate, as in FIG. 23. The connecting mode illustrated herein may beapplied to the active matrix substrate of any of Embodiments 10 to 20 toattain good electrical connection of the substrate to externalterminals.

[0349] [Embodiment 19]

[0350] This is to demonstrate one embodiment for improving thepatterning efficiency in forming TFT of the invention on large-areaglass substrates.

[0351] Where fine semiconductor circuits are formed on large-area glasssubstrates, there occurs a problem of patterning error doe to warping orshrinkage of glass substrates. To solve this problem, specifically notedis an exposing method where is used an exposing device of a so-calledstepper. In stepper exposure, only a part of one reticule 90 can beselectively exposed.

[0352] In this Embodiment, the necessary circuit patterns for the drivercircuit and the pixel matrix circuit are formed in different portions ofone reticule. In this case, the region for the repetition of one and thesame structure is formed through repetitive exposure for one and thesame circuit pattern.

[0353]FIG. 24 is referred to, in which patterns A, C, G and I arecircuit patterns for forming the edges of the driver circuit; patterns Band H are repetitive circuit patterns for the driver circuit to bescanned horizontally; patterns D and F are repetitive circuit patternsfor the driver circuit to be scanned vertically; and a pattern E is arepetitive circuit pattern for the pixel matrix circuit.

[0354] In that manner, for the driver circuit and the pixel matrixcircuit that are comprising repetitive circuits having the samestructure unit, only their edges are formed of their own independentcircuit patterns while their inside areas are formed of one and the samecircuit pattern unit to be repeated, and these are combined to give thecomplete patterns.

[0355] In this system, the same circuit pattern units may be used informing the complete patterns. Therefore, in this, the number of thecircuit pattern units to be written in one reticule may be reduced, andthe size of the reticule to be used may be reduced. In addition, inthis, since one reticule can be repeatedly used many times forlarge-area substrates, the time for mask changing is reduced and thethroughput of the device formed is increased.

[0356] For example, for a pixel matrix circuit of SXGA, 1280 pixels arealigned in rows and 1024 pixels in columns. For this, the patterncircuits corresponding to 256 pixels may be written in rows for thepattern E, and five repetitive exposures may be done for those rows;while the pattern circuits corresponding to 256 pixels may be written incolumns, and four repetitive exposures may be done for those columns.

[0357] In this system where the number of repetitive exposures in rowsand in columns are represented by n and m, respectively, while thenumber of pixels in rows and in columns are by X and Y, respectively,X/n pixel patterns in rows and Y/m patterns in columns must be writtenfor the circuit patterns to form the pixel matrix circuit. According tothis regularity, high-precision displays with 1920×1080 pixels, such asATV (advanced TV), can be easily realized.

[0358] [Embodiment 20]

[0359] This is to demonstrate one embodiment of AMLCD(active-matrix-type liquid crystal display) comprising the active matrixsubstrate of any of Embodiments 10 to 17. The AMLCD of this Embodimentcomprises inverse stagger-type TFT for the driving circuit and the pixelmatrix circuit as formed on one and the same substrate. In this, thebasic structure of the driving circuits is designed on the basis of aCMOS circuit. Therefore, the power for the AMLCD of this Embodiment islow.

[0360]FIG. 25A and FIG. 25B show the outward appearance of the AMLCD ofthis Embodiment. In FIG. 25A, 1101 is an active matrix substrate, onwhich is mounted a TFT of the invention that comprises a pixel matrixcircuit 1102, a source driving circuit 1103 and a gate driving circuit1104. In this, 1105 is a counter substrate.

[0361] The active matrix substrate 1101 and the counter substrate 1105are stuck together with their one end being aligned. At the other end,the counter substrate 1105 is partly cut, and FPC (flexible printcircuit) 1106 is connected with the exposed area of the active matrixsubstrate. Via the FPC 1106, external information is transmitted intothe inside of the circuit.

[0362] On the exposed area of the active matrix substrate connected withthe FPC 1106, mounted are IC chips 1107 and 1108. These IC chipscomprise various circuits, such as video information-processing circuit,timing pulse-generating circuit, -co rrecting circuit, memory circuit,arithmetic circuit, etc., as formed on silicon substrates. In FIG. 25C,two IC chips are mounted on the active matrix substrate. However, one ICchips or three or more IC chips may be mounted thereon.

[0363]FIG. 25B is another modification of AMLCD of this Embodiment. InFIG. 25A and FIG. 25B., the same parts are represented by the samenumeral references. The embodiment of FIG. 25A differs from that of FIG.25A in that the signal information as processed by the IC chips in FIG.25A is processed by the logic circuit 1109 of TFT formed on thesubstrate in the embodiment of FIG. 25B.

[0364] In the embodiment of FIG. 25B, the basic structure of the logiccircuit 1109 may be designed on the basis of a CMOS circuit, like thatin the driving circuits 1103 and 1104, for which is used the inversestagger-type TFT of the invention.

[0365] TFT of the invention are usable not only as switching elementsfor AMLCD but also as those for EL (electroluminescent) display devices.In addition, bottom-gate-type TFT of the invention are usable incircuits for image sensors, etc.

[0366] As in the above, TFT of the invention are applicable to variouselectro-optical devices. The terminology “electro-optical device” asreferred to herein includes any and every device for converting electricinformation into optical information and vice verse.

[0367] In the AMLCD of this Embodiment, the black matrices may be formedon the counter substrate, or on the active matrix substrate (BM on TFT).

[0368] Color filters may be used for color imaging through the device ofthis Embodiment. Without using color filters, the liquid crystalmolecules in the device of this Embodiment may be driven in ECB(electric field control birefringence) mode, GH (guest-host) mode or thelike.

[0369] Like the technique disclosed in Japanese Patent ApplicationLaid-Open (JP-A) Hei-815686, the device of this Embodiment may becombined with a micro-lens array.

[0370] [Embodiment 21]

[0371] AMLCD of Embodiment 20 is usable as the display in variouselectronic instruments. Electronic instruments as referred to herein aredirected to those comprising electro-optical devices such as typicallyAMLCD.

[0372] The electronic instruments include video cameras, still cameras,projectors, projection TV, head-mount displays, car navigations,personal computers (including notebook-type ones), portable informationterminals (mobile computers, portable telephones, etc.), etc. Someexamples of those electronic instruments are shown in FIG. 26A to FIG.26F.

[0373]FIG. 26A is a portable telephone. Its body 2001 is provided with avoice-outputting member 2002, a voice-inputting member 2003, a displaydevice 2004, a control switch 2005, and an antenna 2006. In this, theinvention is applicable to the display device 2004, etc.

[0374]FIG. 26B is a video camera. Its body 2101 is provided with adisplay device 2102, a voice-inputting member 2103, a control switch2104, a battery 2105, and an image-receiving member 2106. In this, theinvention is applicable to the display device 2102.

[0375]FIG. 26C is a mobile computer. Its body 2201 is provided with acamera member 2202, an image-receiving member 2203, a control switch2204, and a display device 2205. In this, the invention is applicable tothe display device 2205, etc.

[0376]FIG. 26D is a head-mount display. Its body 2301 is provided with adisplay device 2302, and a band member 2303. In this, the invention isapplicable to the display device 2302.

[0377]FIG. 26E is a rear projector. Its body 2401 is provided with alight source 2402, a display device 2403, a polarized beam splitter2404, reflectors 2405 and 2406, and a screen 2407. In this, theinvention is applicable to the display device 2403.

[0378] FIG. F is a front projector. Its body 2501 is provided with alight source 2502, a display device 2503, an optical system 2504, and ascreen 2505. In this, the invention is applicable to the display device2503.

[0379] As in the above, the present invention has extremely broadapplication ranges, and is applicable to various electronic instrumentsin various fields. Apart from the examples noted above, the invention isapplicable to light bulletin boards, advertising propaganda displays,etc.

[0380] [Embodiment 22]

[0381] This is to demonstrate one embodiment of the constitution of acircuit comprising the inverse stagger-type TFT of the invention. Hereinreferred to are FIG. 27A and FIG. 27B that illustrate the constitutionof a shift register circuit. In this Embodiment, employed is the layerstructure of Embodiment 10.

[0382]FIG. 27A shows a circuit pattern of one stage of a shift registercircuit, and FIG. 27B shows the equivalent circuit pattern of the shiftregister circuit. In this Embodiment, the positional relationshipbetween FIG. 27A and FIG. 27B nearly corresponds to each other.Therefore,, the reference codes in FIG. 27B are referred to in FIG. 27A.

[0383] In FIG. 27A, the circuit comprising TFT (a) to TFT (d) and TFT(g) to TFT (j) is a clocked inverter circuit; and the circuit comprisingTFT (e) and TFT (f) is an inverter circuit. TFT (e) has a double-gatestructure.

[0384] In this, 1201 is a CLK line (clock signal line), 1202 is aninverse CLK line (inverse clock signal line), 1203 is a GND wiring line(ground line), and 1204 is a Vdd line (power source line). Those wiringpatterns as shadowed with lines rising to the left are all second wiringlayers (indicated by 45 to 49 in FIG. 13A).

[0385] The wiring 1205 functions as the gate electrode of TFT (a). Thewiring patterns as shadowed with lines rising to the right are all firstwiring layers (indicated by 32 to 35 in FIG. 12A). The area in which thefirst wiring layer overlaps with the semiconductor layer is referred toas the gate electrode.

[0386] In the constitution of this Embodiment, overlapping regions (ovin FIG. 27B) are provided in the source side of TFT, while mask offsetregions (of in FIG. 27B) are in the drain side thereof. Accordingly, inFIG. 27B, the clocked inverter circuit comprising TFT (a) to TFT (d) hasa constitution of ov/of/ov/of/of/ov/of/ov in that order from the top.

[0387] Specifically, the structure of the part of TFT (a) and TFT (b) isnearly the same as the double-gate structure of the pixel TFT inEmbodiment 10, and therefore this part has a repetition of ov/of/ov/of.On the other hand, the part of TFT (b) and TFT (c) has a CMOS structurein which the drain electrode is common to NTFT and PTFT. Therefore, asin Embodiment 5, this part has a repetition of ov/of/of/ov.

[0388] The other circuits are basically the same as above. TFT (e) has adouble-gate structure, and therefore has a repeated TFT structure ofov/of/ov/of in that order from its side to which it is connected withthe GND line 1203.

[0389] As having the constitution noted above, the semiconductor circuitof this Embodiment has high voltage resistance and high reliabilitywithout sacrificing its operating motion speed. Using the semiconductorcircuit of the type of this Embodiment in electro-optical devicesimproves the reliability of the devices.

[0390] [Embodiment 23]

[0391] This is to demonstrate another embodiment of the constitution ofa circuit comprising the inverse stagger-type TFT of the invention.Herein referred to are FIG. 28A and FIG. 28B that illustrate theconstitution of a buffer circuit (the left side of the drawings) and ananalog switch circuit (the right side of the drawings). In thisEmbodiment, employed is the layer structure of Embodiment 20. FIG. 28Ashows a circuit pattern, and FIG. 28B shows the equivalent circuitpattern of FIG. 28A.

[0392] In FIG. 28(A), TFT (a′) to TFT (h′) are TFT of the invention. Inthis, TFT (a′) and TFT (c′), and TFT (b′) and TFT (d′) form one buffercircuit each. Like the pixel matrix circuit, the buffer circuit isdriven at a highest operating voltage in liquid crystal display devices,and is therefore required to have high voltage resistance.

[0393] TFT (e′) and TFT (f′), and TFT (g′) and TFT (h′) (pairs for PTFT)form one analog switch circuit each. Also like the pixel matrix circuit,the analog switch circuit is driven at a highest operating voltage inliquid crystal display devices, and is therefore required to have highvoltage resistance.

[0394] First referred to herein is the buffer circuit comprising TFT(a′) and TFT (c′). 1201 is a source electrode (Vdd line) for TFT (a′);1202 is a source electrode (GND line) for TFT (c′); 1203 is a commondrain electrode (output signal line) for TFT (a′) and TFT (c′); and 1204is a common gate electrode (input signal line) for the two TFT.

[0395]1205 is a first conductive layer (n⁺ layer) in the side of thedrain region; 1206 is a first conductive layer (n⁺ layer) in the side ofthe source region; and 1307 is a thin i-layer. TFT (c′) has the samestructure as above, except that a p⁺⁺ layer is substituted for the n⁺layer.

[0396] The buffer circuit has the structure of Embodiment 5 in order tohave high voltage resistance. Specifically, in this circuit, anoverlapping region (ov) is formed in the source side and a mask offsetregion (of) is in the drain side. In that condition, only the drainregion is made to have high voltage resistance, while the resistancecomponent in the source region is reduced.

[0397] The same structure can apply to the buffer circuit comprising TFT(b′) and TFT (d′).

[0398] Next referred to is the analog switch circuit comprising TFT (e′)and TFT (f′). The gate electrode 1204 in the buffer circuit noted aboveis connected with the gate electrode for TFT (e′), while the commondrain electrode for TFT (a′) and TFT (c′) is with the gate electrode forTFT (f′).

[0399]1208 and 1210 are common source electrodes (input data signallines) in the analog switch circuit; and 1209 is a common drainelectrode (output data signal line). The electrode 1208 is for TFT (e′)and TFT (f′); while the electrode 1210 is for TFT (g′) and TFT (h′).These electrodes 1208 and 1210 transmit different image signals.

[0400] In this structure, when any one of TFT (e′) or TFT (f) is “ON”,the data signal (image signal) transferred from the input data signalline 1208 is transmitted to the pixel matrix circuit via the output datasignal line 1209. Therefore, also in TFT (e′) and TFT (f′) constitutingthe analog switch circuit, a mask offset region is provided in the drainside and an overlapping region is in the source side.

[0401] The same structure can apply to the buffer circuit comprising TFT(g′) and TFT (h′).

[0402] [Embodiment 24]

[0403] This embodiment shows an example in which at the formation stepsof the gate insulating film and the semiconductor film (amorphoussilicon film) in the manufacturing steps of each Embodiment 1 toEmbodiment 26, the respective films are continuously formed withoutbeing exposed to the atmosphere.

[0404] As a method of forming the gate insulating film and thesemiconductor film, any method such as plasma CVD method and sputteringmethod can be employed. However, it is important to preventcontamination materials of the atmosphere (oxygen, boron, metal elementsor the like) from attaching to the interface between the gate insulatingfilm and the semiconductor film by avoiding exposure of the films to theatmosphere. In this embodiment, a multi-chamber (for instance, a deviceshown in FIG. 29) that is provided with an exclusive chamber for formingthe gate insulating film and an exclusive chamber for forming startingsemiconductor film, is used, and by moving each chamber, the gateinsulating film and the semiconductor film are continuously formed so asto form a lamination without being exposed to the atmosphere.Incidentally, it is preferable to reduce the contamination material onthe surface, where the semiconductor film is to be formed, by means ofactive hydrogen or hydrogen compounds before forming the semiconductorfilm.

[0405]FIG. 29 schematically shows a device (a continuous film formationsystem) viewed from the top thereof, which will be described in thisembodiment. In FIG. 29, reference numerals 2912-2916 denote chambershaving air-tight property. A vacuum discharge pump and an inert gasintroducing system are arranged in each chamber.

[0406] The present embodiment is applied to the cases in which the gateinsulating film and the semiconductor film of Embodiment 1 are formed.

[0407] Chambers denoted by 2912 and 2913 serve as load-lock chambers forcarrying a sample (substrate to be processed) 2910 into the system.Reference numeral 2914 denotes a first chamber for forming the gateinsulating film (a first layer). Numeral 2915 denotes a second chamberfor forming the gate insulating film (a second layer). Numeral 2916denotes a third chamber for forming the semiconductor film (amorphoussilicon film). Also, numeral 2911 denotes a common chamber of thesample, which is disposed commonly to each chamber. Reference numerals2923-2927 denote gate valves of each chamber; 2931, a robot arm; 2933and 2934, cassettes. In this embodiment, the case in which the gateinsulating film has a double-layer structure is shown. It is needless tosay, however, that the present embodiment is also applicable to a casein which the gate insulating film has a single-layer structure, and forexample, to the case in which the gate insulating film is consisted fromsilicon oxide only.

[0408] In this embodiment, in order to prevent the contamination, thegate insulating film and the semiconductor film are formed so as to forma lamination by different chambers from each other utilizing the deviceshown in FIG. 29. It is a matter of course that the device shown in FIG.29 is just an example.

[0409] Also, an arrangement is applicable in which a lamination iscarried out by changing reaction gases within a single chamber. Whenserial film formation is conducted within the single chamber, it ispreferable to reduce the contamination material, in particular, oxygen(because oxygen inhibits the crystallization) on the surface, where thesemiconductor film is to be formed, by means of the active hydrogen orhydrogen compounds before forming the semiconductor film. In this case,degassing is carried out by changing oxygen attached to an inner wall ofthe chamber and electrodes into OH group by utilizing active hydrogen orhydrogen compounds which are generated from plasma process that uses areaction gas such as hydrogen/NH₃, H₂, Ar and He. Accordingly, oxygen isprevented from mixing in upon the formation of the semiconductor film atthe initial stage. Further, at the formation of each film, the sametemperature(50_C) and the same pressure (20%) are preferably used.

[0410] With the above arrangement, contamination of the gate insulatingfilm and the semiconductor film is prevented to thereby realize stableand good electrical characteristics.

[0411] As in the above, using the semiconductor device structure of thepresent invention in semiconductor circuits that are required to havehigh voltage resistance realizes the increase in the reliability of thesemiconductor circuits. This is important for producing electro-opticaldevices of high reliability.

[0412] As has been described in detail hereinabove with reference to itsembodiments, the present invention provides a technique of producing TFTon a mass-production scale in which is used an extremely small number ofmasks (typically, 4 masks).

[0413] According to the present invention, it is possible to formelectric field buffer layers (LDD region, mask offset region, thicknessoffset region, etc.) for absorbing data fluctuations, between thechannel-forming region and the source/drain electrodes in semiconductordevices. Providing the semiconductor devices of that type, therefore,the present invention realizes TFT of high reliability and highreproducibility.

[0414] In addition, the present invention is applicable to semiconductordevices of any and every type, including semiconductor circuitscomprising TFT noted above, electro-optical devices comprising acombination of such semiconductor circuits and liquid crystal layers,etc., and even electronic instruments comprising displays of suchelectro-optical devices.

[0415] While the invention has been described in detail and withreference to specific embodiments thereof, it will be apparent to oneskilled in the art that various changes and modifications can be madetherein without departing from the spirit and scope thereof.

In the claims:
 1. A method for producing a semiconductor device,comprising the steps:
 2. forming a gate electrode, a gate-insulatinglayer, and an amorphous semiconductor film on an insulating surface; 3.exposing the amorphous semiconductor film to laser beams or to intenselight equivalent to laser beams to thereby convert it into asemiconductor film having a crystalline structure;
 4. adding an impurityselected from Group 15 only or from Group 13 and Group 15 to thesemiconductor film having a crystalline structure to form conductivelayers;
 5. forming a source electrode and a drain electrode on theconductive layers, and
 6. etching the semiconductor film having acrystalline structure via the source electrode and the drain electrodeboth acting as masks for the film to thereby form a channel-formingregion.
 7. A method according to claim 1 , further comprising at leastonce a laser annealing step of processing the semiconductor film havinga crystalline structure .
 8. A method according to claim 1 , wherein theimpurity selected from Group 15 is phosphorus, and that from Group 13and Group 15 is boron and phosphorus.
 9. A method according to claim 1 ,wherein the impurity addition is performed through ion implantation orion doping.
 10. A method according to claim 1 , further comprising astep of performing heat treatment through lamp annealing.
 11. A methodaccording to claim 1 , wherein at least said gate insulating film andsaid amorphous semiconductor film are formed continuously.
 12. A methodaccording to claim 6 , wherein the continuous forming steps areperformed in a multi-chamber.
 13. A method according to claim 6 ,wherein the continuous forming steps are performed in a single chamber.14. A method according to claim 1 , wherein the semiconductor device isa display device.
 15. A method according to claim 1 , wherein thesemiconductor device is an electronic instrument selected from the groupconsisting of a video camera, a still camera, a projector, a projectionTV, a head-mount display, a car navigation, a personal computer, amobile computer, and a portable telephone.
 16. A method for producing asemiconductor device, comprising the steps of:
 17. forming a gateelectrode, a gate-insulating layer, and an amorphous semiconductor filmon an insulating surface;
 18. exposing the amorphous semiconductor filmto laser beams or to intense light equivalent to laser beams to therebyconvert it into a semiconductor film having a crystalline structure; 19.adding an impurity selected from Group 15 only or from Group 13 andGroup 15 to the semiconductor film having a crystalline structure toform conductive layers;
 20. forming a source electrode and a drainelectrode on the conductive layers;
 21. etching the semiconductor filmhaving a crystalline structure via the source electrode and the drainelectrode both acting as masks for the film to thereby form achannel-forming region; and
 22. adding an impurity for threshold voltagecontrol to the semiconductor film via the source electrode and the drainelectrode both acting as masks for the film.
 23. A method according toclaim 11 , further comprising at least once a laser annealing step ofprocessing the semiconductor film having a crystalline structure.
 24. Amethod according to claim 11 , wherein the impurity selected from Group15 is phosphorus, and that from Group 13 and Group 15 is boron andphosphorus.
 25. A method according to claim 11 , wherein the impurityaddition is performed through ion implantation or ion doping.
 26. Amethod according to claim 11 , further comprising a step of performingheat treatment through lamp annealing.
 27. A method according to claim11 , wherein at least said gate insulating film and said amorphoussemiconductor film are formed continuously.
 28. A method according toclaim 16 , wherein the continuous forming steps are performed in amulti-chamber.
 29. A method according to claim 16 , wherein thecontinuous forming steps are performed in a single chamber.
 30. A methodaccording to claim 11 , wherein the semiconductor device is a displaydevice.
 31. A method according to claim 11 , wherein the semiconductordevice is an electronic instrument selected from the group consisting ofa video camera, a still camera, a projector, a projection TV, ahead-mount display, a car navigation, a personal computer, a mobilecomputer, and a portable telephone.
 32. A method for producing asemiconductor device, comprising the steps of:
 33. forming a gateelectrode, a gate-insulating layer, and an amorphous semiconductor filmon an insulating surface,
 34. exposing the amorphous semiconductor filmto laser beams or to intense light of which the intensity is equivalentto that of laser beams, to thereby crystallize the film into asemiconductor film having a crystalline structure,
 35. adding animpurity selected from Group 13 and/or Group 15 to the semiconductorfilm having a crystalline structure through ion implantation or iondoping, to thereby form first and second conductive layers containingthe impurity,
 36. exposing the conductive layers to laser beams or tointense light of which the intensity is equivalent to that of laserbeams, to thereby activate the impurity,
 37. forming a source electrodeand a drain electrode on the conductive layers, and
 38. etching thesemiconductor film having a crystalline structure via the sourceelectrode and the drain electrode both acting as masks for the film tothereby form a channel-forming region,
 39. wherein thicknesses of thefirst and second conductive layers are controlled by the concentrationprofile of the impurity.
 40. A method according to claim 21 , whereinthe impurity selected from Group 13 is boron, indium or gallium, andthat from Group 15 is phosphorus, arsenic or antimony.
 41. A methodaccording to claim 21 , wherein at least said gate insulating film andsaid amorphous semiconductor film are formed continuously.
 42. A methodaccording to claim 23 , wherein the continuous forming steps areperformed in a multi-chamber.
 43. A method according to claim 23 ,wherein the continuous forming steps are performed in a single chamber.44. A method according to claim 21 , wherein the semiconductor device isa display device.
 45. A method according to claim 21 , wherein thesemiconductor device is a n electronic instrument selected from thegroup consisting of a video camera, a still camera, a projector, aprojection TV, a head-mount display, a car navigation, a personalcomputer, a mobile computer, and a portable telephone.
 46. A method forproducing a semiconductor device, comprising the steps of:
 47. forming agate electrode, a gate-insulating layer, and an amorphous semiconductorfilm on a substrate having an insulating surface,
 48. exposing theamorphous semiconductor film to laser beams or to intense light of whichthe intensity is equivalent to that of laser beams, to therebycrystallize the film into a semiconductor film having a crystallinestructure,
 49. adding an impurity selected from Group 13 and/or Group 15to the semiconductor film having a crystalline structure through ionimplantation or ion doping, to thereby form first and second conductivelayers containing the impurity,
 50. exposing the conductive layers tolaser beams or to intense light of which the intensity is equivalent tothat of laser beams, to thereby activate the impurity,
 51. forming asource electrode and a drain electrode on the conductive layers, 52.etching the semiconductor film having a crystalline structure via thesource electrode and the drain electrode both acting as masks for thefilm to thereby form a channel-forming region, and
 53. adding to thefilm an impurity for threshold voltage control, via the source electrodeand the drain electrode both acting as masks for the film,
 54. whereinthicknesses of the first and second conductive layers are controlled bythe concentration profile of the impurity.
 55. A method according toclaim 28 , wherein the impurity selected from Group 13 is boron, indiumor gallium, and that from Group 15 is phosphorus, arsenic or antimony.56. A method according to claim 28 , wherein at least said gateinsulating film and said amorphous semiconductor film are formedcontinuously.
 57. A method according to claim 30 , wherein thecontinuous forming steps are performed in a multi-chamber.
 58. A methodaccording to claim 30 , wherein the continuous forming steps areperformed in a single chamber.
 59. A method according to claim 28 ,wherein the semiconductor device is a display device.
 60. A methodaccording to claim 28 , wherein the semiconductor device is anelectronic instrument selected from the group consisting of a videocamera, a still camera, a projector, a projection TV, a head-mountdisplay, a car navigation, personal computer, a mobile computer, and aportable telephone.